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JP-2026514260-A - Method for operating inverters and diode clamp inverters

JP2026514260AJP 2026514260 AJP2026514260 AJP 2026514260AJP-2026514260-A

Abstract

An inverter is described. This inverter is connectable to a DC power source and comprises a DC bus having a first leg and a second leg, a plurality of electronic switches connected in series, wherein the first electronic switch of the electronic switches is connected to the first leg, the second electronic switch of the electronic switches is connected to the second leg, and the plurality of electronic switches define a plurality of intermediate switch nodes between them, a voltage divider connected to the first leg and the second leg, wherein the voltage divider comprises a plurality of capacitors connected in series and defining at least one first partial voltage node, at least one pair of first level clamping diodes, wherein each pair of first level clamping diodes comprises at least two diodes connected in series and defining a diode node between at least two diodes, and the diode node is connected to one of the at least one first partial voltage node. At least one diode of the pair of first level clamping diodes is connected to the intermediate switch node to define a first partial clamp voltage at the intermediate switch node, on the side of the diodes other than the diode node. The inverter further includes at least one flying capacitor connected in parallel with the first level clamping diode pair. The electronic switches are grouped into high-side switches and low-side switches. The control inputs of the high-side switches are functionally connected to switch all of the high-side switches simultaneously, and the control inputs of the low-side switches are functionally connected to switch all of the low-side switches simultaneously. The inverter is configured to generate two-level AC output power. [Selection Diagram] Figure 1

Inventors

  • ロスムンド、ダニエル
  • カナレス、フランシスコ

Assignees

  • アーベーベー・イー－モビリティ・ビー．ブイ．
  • アーベーベー・シュバイツ・アーゲー

Dates

Publication Date
20260507
Application Date
20240503
Priority Date
20230504

Claims (15)

  1. Inverter (100), A DC bus that can be connected to a DC power supply (160) and has a first leg (102) and a second leg (104), A plurality of electronic switches (110, 112, 120, 122) are connected in series, where the first electronic switch (110) is connected to the first leg (102), and the second electronic switch (120) is connected to the second leg (104), and the plurality of electronic switches define a plurality of intermediate switch nodes (115, 125) between them. A voltage divider (155) connected to the first leg (102) and the second leg (104), wherein the voltage divider comprises a plurality of capacitors (150, 152) connected in series and defining at least one first partial voltage node (154), At least one first-level clamping diode pair (135), where each first-level clamping diode pair (135) comprises at least two diodes (130 H , 130 L ) connected in series and defining a diode node (134) between the two diodes (130 H , 130 L ), the diode node (134) being connected to one of the at least one first partial voltage node (154), and at least one diode (130 H , 130 L ) of the first-level clamping diode pair (135) being connected to the intermediate switch node (115, 125) to define a first partial clamp voltage at the intermediate switch node (115, 125) on the side of the diode other than the diode node (134). At least one flying capacitor (140) connected in parallel to the first level clamping diode pair (135), Equipped with, The aforementioned electronic switches (110, 112, 120, 122) are grouped into high-side switches (110, 112) and low-side switches (120, 122). The control input (111) of the high-side switches (110, 112) is functionally connected to switch all of the high-side switches (110, 112) simultaneously. The control input (121) of the low-side switches (120, 122) is functionally connected to switch all of the low-side switches (120, 122) simultaneously. The inverter (100) is configured to generate two-level AC output power.
  2. The inverter according to claim 1, further comprising a control device connected to the control inputs (111, 121) and configured to provide signals for simultaneously switching the high-side switches (110, 112) and the low-side switches (120, 122).
  3. The inverter according to claim 1 or 2, wherein the voltage divider comprises an even number of capacitors, and the at least one first partial voltage node (154) comprises a neutral voltage node.
  4. The at least one pair of first-level clamping diodes (135) defines a second partial clamp voltage at the first-level partial clamp voltage node (254), At least one second-level clamping diode pair (235), wherein the second-level clamping diode pair comprises at least two diodes connected in series and defining a diode node (234) between at least two diodes (230 H , 230 L ), the diode node (234) being connected to the first-level partial clamp voltage node (254), and at least one diode (230 H , 230 L ) of the second-level clamping diode pair being connected to the intermediate switch node (115, 125) to define a third partial clamp voltage at the intermediate switch node (115, 125). At least one flying capacitor (240) connected in parallel to the second level clamping diode pair (235), An inverter according to any one of claims 1 to 3, further comprising the above.
  5. The present invention comprises at least two pairs of second-level clamping diodes (235) according to claim 4 connected in series, each diode node (234 H , 234 L ) connected to a first-level partial clamp voltage node (134 H , 134 L ) having different second partial clamp voltages, The flying capacitor connected in parallel to the second level clamping diode pair is at least two flying capacitors (240 H , 240 L ) connected in series. The inverter according to claim 4.
  6. At least one n-th level clamping diode pair (335), wherein the n-th level clamping diode pair comprises at least two diodes connected in series and defining a diode node (334) between at least two diodes (330, 332), the diode node (334) being connected to an (n-1)-th level partial clamp voltage node, and at least one diode (330, 332) of each n-th level clamping diode pair (335) being connected to an intermediate switch node (115, 125) to define an n-th level partial clamp voltage at the intermediate switch node (115, 125). At least one flying capacitor (340) connected in parallel to the n-level clamping diode pair, Equipped with, Here, n is 2 or more, the inverter according to claim 4 or 5.
  7. The inverter according to any one of claims 1 to 6, wherein one of the first partial voltage nodes is connected to an intermediate switch node.
  8. The voltage divider (155) comprises four capacitors (150, 152, 250, 252) connected in series and defining three partial voltage nodes (154, 154 H , 154 L ), Eight electronic switches (510, 512, 514, 516, 520, 522, 524, 526) are connected in series to the DC bus, A first level clamping diode pair (535 H ) comprising two diodes (530 H , 530 L ) connected in series and defining a first diode node, wherein the first diode node is connected to the first partial voltage node (154 H ) of the three partial voltage nodes, and therein, The first diode (530 H ) of the first first level clamping diode pair (535 H ) is connected to the first intermediate switch node (115 1 ) to define the first partial clamp voltage of the electronic switch (510, 512). The second diode (530 L ) of the first level clamping diode pair (535 H ) is connected to a second intermediate switch node (115 2 ) to define the second partial clamp voltage of the electronic switch (524, 526). A second first-level clamping diode pair (535 L ) comprising two diodes (532 H , 532 L ) connected in series and defining a second diode node, wherein the second diode node is connected to the second partial voltage node (154 L ) of the three partial voltage nodes, and therein, The first diode (532 H ) of the second first-level clamping diode pair (535 L ) is connected to a third intermediate switch node (125 2 ) to define a third partial clamp voltage of the electronic switch (520, 522). The second diode (532 L ) of the second first-level clamping diode pair (535 L ) is connected to a fourth intermediate switch node (125 1 ) to define a fourth partial clamp voltage of the electronic switch (514, 516). The third of the three partial voltage nodes (154) is connected to the fifth intermediate switch node. An inverter (500) according to any one of claims 1 to 7, comprising:
  9. The inverter according to any one of claims 1 to 8, wherein the inverter is configured to switch the power of a DC power supply having a voltage of at least 10 kV and/or a power of at least 100 kW.
  10. The inverter according to any one of claims 1 to 9, wherein the current rating of the diodes in each clamping diode pair is less than 10 A, and/or the capacitance of each of the flying capacitors is less than 500 nF.
  11. The inverter according to any one of claims 1 to 10, wherein the inverter is configured to drive a medium-frequency transformer in two-level operation.
  12. The inverter according to any one of claims 1 to 11, wherein the electronic switch is selected from the group consisting of MOSFET, IGBT, HEMT, and IGCT, and in particular, the electronic switch is rated for a cutoff voltage of less than 1.7 kV.
  13. A method for operating a diode clamp inverter, wherein the diode clamp inverter is A plurality of electronic switches (110, 112, 120, 122) connected in series, wherein the first electronic switch (110) is connected to the first leg (102) of the DC bus, the second electronic switch (120) is connected to the second leg (104) of the DC bus, and the electronic switches (110, 112, 120, 122) are grouped into high-side switches (110, 112) and low-side switches (120, 122). At least one first-level clamping diode pair (135), where each first-level clamping diode pair (135) comprises at least two diodes (130 H , 130 L ) connected in series and defining a diode node (134) between the two diodes (130 H , 130 L), wherein at least one diode (130 H , 130 L ) of the first-level clamping diode pair ( 135 ) is connected to the intermediate switch node (115, 125) to define a first partial clamp voltage at the intermediate switch node (115, 125) on the side of the diode other than the diode node (134). The method comprises, A flying capacitor (140) is provided in parallel with at least one pair of clamping diodes, Switching all high-side switches (110, 112) simultaneously, Switching all low-side switches (120, 122) simultaneously, By switching the aforementioned high-side switch and/or the aforementioned low-side switch, two-level AC output power is generated, A method that includes [a certain feature].
  14. The method according to claim 13, comprising: operating the high-side switch so that the high-side switch is functionally similar to a single switch; and operating the low-side switch so that the low-side switch is functionally similar to a single switch.
  15. The method according to claim 14, further comprising driving a medium-frequency transformer with the output power.

Description

Aspects of the present invention relate to inverters, particularly power inverters, and especially power inverters suitable for medium-voltage and/or high-voltage applications. The present invention particularly relates to the operation of a diode clamp inverter having a plurality of electronic switches connected in series. A power inverter is typically an electronic circuit for generating alternating current (AC) from a direct current (DC) source. Inverters can be particularly useful in transformerless converters and/or converters such as solid-state transformers. Such converters are becoming increasingly important due to advancements in fields such as electrified transportation, supercomputing and data centers, renewable energy production, transmission, and utilization, as well as many other industrial sectors requiring power conversion. Furthermore, inverters can be used to drive machinery such as electric motors. Advantageously, compared to other solutions, inverter-based circuits can have higher power density and allow for improved control of the generated output power. Inverters often utilize electronic switches, such as power semiconductor switches, to generate the desired output power. With increasing power demand, inverters suitable for switching voltages exceeding 200 volts, medium voltages, and even high voltages are becoming increasingly important. However, semiconductor switches with the required cutoff voltage can be expensive and/or have other performance drawbacks, such as undesirable frequency response, higher internal resistance, and/or limited operating life. The document ADAM G P ET AL: “Capacitor Balance Issues of the Diode-Clamped Multilevel Inverter operated in a Quasi Two-State mode”, IEEE TRANSACTIONS ON INDUSTRIAL ELECRONICS, IEEE SERVICE CENTER, vol. 55, no 8, 1 August 2008, pages 3088-3099, XP011232121, ISSN: 0278-0046, DOI: 10.1109/TIE.2008.922607 describes a diode-clamped multilevel inverter. The voltage across each switching device is clamped to a capacitor divider through a diode network. This circuit operates in multilevel mode, utilizing a series capacitor bank to provide an intermediate output voltage level. Alternatively, a quasi-two-level modulation technique is used for output voltage synthesis. Reference WO 2023/031346 A1 describes a flying capacitor converter having a non-dissipative voltage balancing circuit for charging the converter's flying capacitor. Charging of C1 is achieved through the (internal) antiparallel diode S B, b1 . Discharging of C1 can be achieved by switching the balancing switch S B, a1 in synchronization with the main semiconductor switch S 2b , so that the flying capacitor C1 is connected in parallel with the DC bus capacitor C iYZ . Reference EP 3 197 033 A1 describes methods and equipment for removing harmonics based on two complementary techniques: selective harmonic rejection (SHE PWM) through pulse width modulation combined with a multi-wiring transformer. Therefore, improved inverters, particularly those suitable for use at medium or high voltages, are needed. Taking the above into consideration, the present invention as described in the attached claims is provided. In one embodiment, an inverter is described. This inverter is connectable to a DC power source and includes a DC bus having a first leg and a second leg, a plurality of electronic switches connected in series, wherein the first electronic switch of the electronic switches is connected to the first leg, the second electronic switch of the electronic switches is connected to the second leg, and the plurality of electronic switches define a plurality of intermediate switch nodes between them, a voltage divider connected to the first leg and the second leg, wherein the voltage divider comprises a plurality of capacitors connected in series and defining at least one first partial voltage node, and at least one diode of the first level clamping diode pair, wherein each first level clamping diode pair comprises at least two diodes connected in series and defining a diode node between at least two diodes, and the diode node is connected to one of the at least one first partial voltage node, and at least one diode of the first level clamping diode pair is connected to an intermediate switch node to define a first partial clamp voltage at an intermediate switch node on the side of the diode other than the diode node. The inverter further includes at least one flying capacitor connected in parallel with the first level clamping diode pair. The electronic switches are grouped into high-side switches and low-side switches. The control inputs of the high-side switches are functionally connected to switch all of the high-side switches simultaneously, and the control inputs of the low-side switches are functionally connected to switch all of the low-side switches simultaneously. The inverter (100) is configured to generate two-level AC output power. In one embodiment, a method for operating a