Search

JP-2026514271-A - Piezoelectric on-insulator (POI) substrate and process for manufacturing piezoelectric on-insulator (POI) substrate

JP2026514271AJP 2026514271 AJP2026514271 AJP 2026514271AJP-2026514271-A

Abstract

The present invention relates to a piezoelectric on-insulator (POI) substrate (130) comprising a carrier substrate (100) having a trap layer (102) on the free surface (104) of the carrier substrate (100), a piezoelectric layer (106), and an intermediate structure (110) sandwiched between the piezoelectric layer (106) and the trap layer (102) of the carrier substrate (100), wherein the intermediate structure ( 120 ) includes at least one aluminum oxide ( Al₂O₃ )-based diffusion barrier layer (122) having a thickness t EM greater than a predetermined thickness, and the predetermined thickness is determined according to the thickness of the trap layer (102) such that the dose of metal elements in the trap layer (102) is lower than a predetermined threshold dose. The present invention also relates to a process for manufacturing a piezoelectric on-insulator (POI) substrate (130).

Inventors

  • アレクシス ドルーアン
  • イザベル フイエ
  • オレグ クノンチュク
  • マルセル ブルーカート
  • ルチアナ カペッロ
  • ブリス タヴェル

Assignees

  • ソイテック

Dates

Publication Date
20260508
Application Date
20231026
Priority Date
20221026

Claims (14)

  1. A piezoelectric on-insulator (POI) substrate, A carrier substrate (100), which is particularly a silicon-based substrate, and which includes a trap layer (102), particularly a polycrystalline, amorphous, or porous silicon-based layer, on the free surface (104) of the carrier substrate (100), Piezoelectric layer (114), particularly lithium tantalate (LTO) layer or lithium niobate (LNO) layer, An intermediate structure (120, 120') sandwiched between the piezoelectric layer (114) and the trap layer (102) of the carrier substrate (100), wherein the intermediate structure (120, 120') includes at least one barrier layer (122, 122 ') having a thickness t EM greater than a predetermined thickness for preventing the diffusion of aluminum oxide ( Al₂O₃ )-based metal elements, particularly lithium, wherein the predetermined thickness is determined according to the thickness of the trap layer (102) such that the amount of metal element dose in the trap layer (102), particularly lithium dose, is less than a predetermined threshold dose, particularly less than 1.2 × 10¹² at/ cm² , particularly less than 5 × 10¹¹ at/ cm² , and more specifically less than lithium threshold dose. A piezoelectric on-insulator (POI) substrate equipped with the following features.
  2. The piezoelectric on-insulator (POI) substrate according to claim 1, wherein the metal element diffusion barrier layer (122, 122') has a thickness t EM of 5 nm to 1500 nm, particularly 10 nm to 100 nm, and the thickness t p of the trap layer (102) is 5 nm to 5 μm.
  3. The piezoelectric on-insulator (POI) substrate according to claim 1 or 2, wherein the intermediate structure (120, 120') includes at least one dielectric layer (132, 132') of a silicon dioxide, silicon nitride (SiN), or silicon oxynitride ( SiO₂xNy ) system, in contact with the at least one metal element diffusion barrier layer (122, 122').
  4. The piezoelectric on-insulator (POI) substrate according to any one of claims 1 to 3, wherein the metal element diffusion barrier layer (122') is sandwiched between two dielectric layers (132', 146).
  5. The piezoelectric on-insulator (POI) substrate according to any one of claims 1 to 4, wherein the intermediate structure (120, 120') further comprises a second barrier layer (154, 156, 158, 160).
  6. The piezoelectric on-insulator (POI) substrate according to claim 5, wherein the second barrier layer (154) is a hydrogen diffusion barrier layer (156) of the silicon nitride ( SiN ), silicon oxynitride ( SiO₂xNy ), or aluminum nitride (AlN) type.
  7. The piezoelectric on-insulator (POI) substrate according to any one of claims 1 to 6 , wherein the intermediate structure (120, 120') comprises at least one layer (158) having a hydrogen concentration of less than 10¹⁰ at / cm³ , particularly less than 10¹⁸ at/cm³.
  8. A method for manufacturing a piezoelectric on-insulator (POI) substrate (130, 138, 144, 152, 160) according to any one of claims 1 to 7, The steps include providing a carrier substrate (100), particularly a silicon-based substrate, which includes a trap layer (102), particularly a polycrystalline, amorphous, or porous silicon-based layer, The steps include providing a substrate including a piezoelectric layer (106), particularly a piezoelectric layer (108) based on lithium tantalate (LTO) or lithium niobate (LNO), A step of forming an intermediate structure (120, 120') on the substrate and/or the carrier substrate (100) including a piezoelectric layer (106), wherein the formation of the intermediate structure (120, 120') includes forming at least one diffusion barrier layer (122 , 122') of an aluminum oxide ( Al₂O₃ ) system having a thickness t EM greater than a predetermined thickness and preventing the diffusion of metallic elements, particularly lithium, the predetermined thickness being determined according to the thickness of the trap layer (102) such that the amount of metallic element dose in the trap layer (102), particularly lithium dose, is less than a predetermined threshold dose, particularly less than a threshold metallic element dose, and more specifically less than 1.2 × 10¹² at/ cm² , particularly less than 5 × 10¹¹ at/ cm² . A method comprising the steps of: - assembling the substrate including the piezoelectric layer (106) with the carrier substrate (100).
  9. The step of forming the intermediate structure (120, 120') further comprises forming a second barrier layer (154, 156, 158, 160), a process for manufacturing a piezoelectric on-insulator (POI) substrate (138, 152, 160) according to claim 8.
  10. A process for manufacturing a piezoelectric on-insulator (POI) substrate (138, 152 , 160) according to claim 8 or 9 , wherein the step of forming the intermediate structure (120, 120') further comprises the step of forming a layer (158) having a hydrogen concentration of less than 10¹⁰ at/ cm³ , particularly less than 10¹⁸ at/cm³.
  11. A process for manufacturing a piezoelectric on-insulator (POI) substrate (138, 152, 160 ) according to claim 9 or claim 10 in combination with claim 9, wherein the step of forming the second barrier layer (154) comprises forming a silicon nitride (SiN), silicon oxynitride ( SiO₂xNy ), or aluminum nitride (AlN) based layer (156).
  12. A process for manufacturing a piezoelectric on-insulator (POI) substrate (130, 138, 144, 152, 160) according to any one of claims 8 to 11, further comprising the step of forming dielectric layers (132, 146) on the carrier substrate (100) and/or on the substrate including the piezoelectric layer (106) prior to the assembly step, such that the bonding interface is an oxide-oxide bonding interface.
  13. A process for manufacturing a piezoelectric on-insulator (POI) substrate (130, 138, 144, 152, 160) according to any one of claims 8 to 11, further comprising the step of forming a dielectric layer (132, 146) of a second material different from the first material on the carrier substrate (100) and/or on the substrate including the piezoelectric layer (106), prior to the assembly step.
  14. A process for manufacturing a piezoelectric on-insulator (POI) substrate (130, 138, 144, 152, 160) according to claim 13, wherein the first material is silicon nitride, particularly of the Si3N4 system , and the second material is silicon oxynitride ( SiOxNy ), particularly of the SiON system.

Description

This invention relates to a piezoelectric-on-insulator (POI) substrate and a process for manufacturing such a piezoelectric-on-insulator (POI) substrate. Piezoelectric on-insulator (POI) substrates achieve superior performance compared to other substrates in the prior art, thanks to better values of quality Q and electromechanical coefficient k, and are therefore used in acoustic devices such as sensors and filters. Such a substrate contains a thin layer of piezoelectric material on a dielectric layer, where the dielectric layer itself is located on the carrier substrate. In certain applications, a trapping layer is placed between the carrier substrate and the dielectric layer. The trapping layer is typically an amorphous layer with structural defects such as dislocations, grain boundaries, amorphous regions, gaps, inclusions, and/or pores. These structural defects act as traps for charges that can circulate within the material. Therefore, the trapping layer has high resistivity, resulting in reduced charge conduction within the layer and consequently reducing the current within the trapping layer. The trapping layer reduces losses due to parasitic conduction effects at the interface between the carrier substrate and the dielectric layer. In fact, the trapping layer works to reduce the lifetime of charges in this region. When manufacturing such piezoelectric on-insulator (POI) substrates, a donor substrate is used, on which a piezoelectric material substrate is bonded to a handling substrate. Next, the donor substrate undergoes a thinning step to form a thinner piezoelectric layer before bonding to the carrier substrate. Finally, the transfer of the piezoelectric thin film onto the carrier substrate is performed mechanically or thermally at pre-formed fracture zones in the piezoelectric layer of the donor substrate. A final heat treatment of the resulting substrate (POI) is required to repair any damage to the piezoelectric layer transferred during the fracture step. However, this final annealing process leads to the diffusion of metallic elements (Li, Fe, Cu, Ni) from the piezoelectric layer into the trap layer. Upon diffusion into the trap layer, these metallic elements neutralize (occupy) the electrical traps present within it. This neutralization of electrical traps in the trap layer degrades its electrical performance, particularly its Q factor and radio frequency performance, resulting in a decrease in the electrical performance of the resulting POI substrate. Therefore, one objective of the present invention is to improve upon the aforementioned drawbacks, and in particular, to design a piezoelectric on-insulator (POI) substrate having improved characteristics for use in acoustic devices. The object of the present invention is a piezoelectric on-insulator (POI) substrate comprising: a carrier substrate, particularly a silicon-based substrate, comprising a carrier substrate having a trap layer, particularly a polycrystalline, amorphous, or porous silicon-based layer on the free surface of the carrier substrate; a piezoelectric layer, particularly a layer of lithium tantalate ( LiTaO3 ) or lithium niobate ( LiNbO3 ); and an intermediate structure sandwiched between the piezoelectric layer and the trap layer of the carrier substrate, wherein the intermediate structure comprises at least one aluminum oxide ( Al2O5 )-based diffusion barrier layer for a metal element, particularly lithium, having a thickness t EM greater than a predetermined thickness, the predetermined thickness being determined as a function of the thickness of the trap layer such that the dose of metal elements in the trap layer is less than a predetermined threshold dose, particularly less than 1.2 × 10¹² at/ cm² , particularly less than 5 × 10¹¹ at/cm² . The presence of a metal element diffusion barrier structure between the piezoelectric layer and the trap layer reduces the diffusion of metal elements from the piezoelectric layer to the trap layer during the manufacturing process. In this way, the neutralization of charge traps in the trap layer by metal elements is reduced. Therefore, the trap layer in the final substrate (POI) has high resistivity, resulting in a substrate (POI) with improved performance. The threshold thickness of the barrier layer is determined as a function of the thickness of the trap layer and the threshold dose of metallic elements present in the trap layer, which ensures the trap layer still possesses the electrical properties necessary to obtain an improved POI substrate. According to a modified embodiment of the present invention, the barrier layer can have a thickness of 5 nm to 1.5 μm, particularly 10 nm to 100 nm, and the trap layer has a thickness of 5 nm to 5 μm. The barrier layer is much thinner than the trap layer. According to one modification of the present invention, the intermediate structure may include at least one dielectric layer, particularly of a silicon dioxide, silicon nitride (SiN), or