JP-2026514295-A - NAND's integrated solution for deep contact gap filling

Abstract

A method for filling a via having a necking point includes the steps of: performing a pre-cleaning process to remove residue from the exposed surface of the metal layer at the bottom of the via and to restore the inner surface of the via, wherein the via is formed in a dielectric layer and has a necking point protruding into the via; performing a selective deposition process to partially fill the via with a metal filler material from the exposed surface of the metal layer below the necking point; performing a liner deposition process to form a liner layer on the exposed inner surface of the via; and performing a metal filling process to fill the via with a metal filler material. [Selection Diagram] Figure 4D

Inventors

• ツェン シ
• タン シャンミン
• ウー カイ
• シュー ヤオ
• リ ヤン
• ズー メン
• ハ インス
• グオ ジャンチウ
• リ チャオ
• ワン ロンジュン

Assignees

• アプライド マテリアルズ インコーポレイテッド

Dates

Publication Date

20260508

Application Date

20240122

Priority Date

20230220

Claims (20)

1. A method for filling vias having a necking point, A step of performing a pre-cleaning process to remove residue from the exposed surface of the metal layer at the bottom of the via and to restore the inner surface of the via, wherein the via is formed in a dielectric layer and has a necking point protruding into the via, A step of performing a selective deposition process to partially fill the via with metal filler material from the exposed surface of the metal layer below the necking point, The steps include: performing a liner deposition process to form a liner layer on the exposed inner surface of the via; A method comprising the step of performing a metal filling process to fill the via with the metal filling material.
2. The via has a width of 160 nm to 240 nm and a depth of 5 μm to 20 μm. The necking point protrudes into the via by 100 nm to 120 nm in height from the bottom of the via, which is 800 nm to 1.2 μm in thickness. The method according to claim 1.
3. The metal filling material comprises tungsten (W) or molybdenum (Mo), The liner layer contains titanium nitride (TiN), The dielectric layer includes silicon oxide ( SiO₂ ), silicon nitride ( Si₃N₄ ), silicon oxynitride ( SiO₂xNy ), hafnium -containing material, zirconium-containing material, aluminum-containing material, lanthanum-containing material, or a combination thereof. The method according to claim 1.
4. The method according to claim 1, wherein the pre-cleaning process includes a chemical immersion process in which the exposed surface of the metal layer is immersed in a precursor containing tungsten fluoride ( WF6 ) or hydrogen ( H2 ) provided in a processing chamber.
5. The method according to claim 1, wherein the pre-cleaning process includes an inductively coupled plasma (ICP) process using a plasma formed from a process gas containing a hydrogen ( H₂ ) gas.
6. The method according to claim 1, wherein the pre-cleaning process includes a plasma treatment process using a plasma formed from a process gas containing an oxygen ( O₂ ) gas.
7. The method according to claim 1, wherein the selective deposition process comprises a chemical vapor deposition (CVD) process using a tungsten (W)-containing precursor and a hydrogen ( H₂ )-containing carrier gas, and the flow rate ratio of the tungsten (W)-containing precursor to the hydrogen ( H₂ )-containing carrier gas is 0.001 to 0.007.
8. The method according to claim 1, wherein the metal filling process comprises a chemical vapor deposition (CVD) process using a tungsten (W)-containing precursor, a hydrogen ( H₂ )-containing carrier gas, and a nitrogen-containing gas.
9. A method for filling vias having a necking point, A step of performing a liner deposition process to form a liner layer on the exposed inner surface of a via, wherein the via is formed within a dielectric layer and has a necking point protruding into the via; The steps include performing a liner pullback process to remove the liner layer above the necking point, A step of performing a selective deposition process to partially fill the via with metal filler material from the exposed surface of the liner layer below the necking point, A method comprising the step of performing a metal filling process to fill the via with the metal filling material.
10. The metal filling material comprises tungsten (W) or molybdenum (Mo), The liner layer contains titanium nitride (TiN), The dielectric layer includes silicon oxide ( SiO₂ ), silicon nitride ( Si₃N₄ ), silicon oxynitride ( SiO₂xNy ), hafnium -containing material, zirconium-containing material, aluminum-containing material, lanthanum-containing material, or a combination thereof. The method according to claim 9.
11. The method according to claim 9, further comprising the step of performing a pre-washing process to restore the inner surface of the via prior to the selective deposition process.
12. The method according to claim 11, wherein the pre-cleaning process includes a plasma treatment process using a plasma formed from a process gas containing an oxygen ( O₂ ) gas.
13. The method according to claim 9, wherein the selective deposition process comprises a chemical vapor deposition (CVD) process using a tungsten (W)-containing precursor and a hydrogen ( H₂ )-containing carrier gas, the flow rate ratio of the tungsten (W)-containing precursor to the hydrogen ( H₂ )-containing carrier gas is 0.001 to about 0.007.
14. The method according to claim 9, wherein the metal filling process comprises a chemical vapor deposition (CVD) process using a tungsten (W)-containing precursor, a hydrogen ( H₂ )-containing carrier gas, and a nitrogen-containing gas.
15. A method for filling vias having a necking point, A step of performing a liner deposition process to form a liner layer on the exposed inner surface of a via, wherein the via is formed within a dielectric layer and has a necking point protruding into the via; The steps include performing a liner pullback process to remove the liner layer above the necking point, The steps include: performing a fluorine-free tungsten (FFW) growth process to selectively form a metal capping layer on the exposed surface of the liner layer; A step of performing a selective deposition process to partially fill the via with metal filler material from the exposed surface of the metal capping layer below the necking point, A method comprising the step of performing a metal filling process to fill the via with the metal filling material.
16. The metal filling material comprises tungsten (W) or molybdenum (Mo), The liner layer contains titanium nitride (TiN), The dielectric layer includes silicon oxide ( SiO₂ ), silicon nitride ( Si₃N₄ ), silicon oxynitride ( SiO₂xNy ), hafnium -containing material, zirconium-containing material, aluminum-containing material, lanthanum-containing material, or a combination thereof. The method according to claim 15.
17. The method according to claim 15, further comprising the step of performing a pre-washing process to restore the inner surface of the via prior to the selective deposition process.
18. The method according to claim 17, wherein the pre-cleaning process includes a plasma treatment process using a plasma formed from a process gas containing an oxygen ( O₂ ) gas.
19. The method according to claim 15, wherein the selective deposition process comprises a chemical vapor deposition (CVD) process using a tungsten (W)-containing precursor and a hydrogen ( H₂ )-containing carrier gas, and the flow rate ratio of the tungsten (W)-containing precursor to the hydrogen ( H₂ )-containing carrier gas is 0.001 to 0.007.
20. The method according to claim 15, wherein the metal filling process comprises a chemical vapor deposition (CVD) process using a tungsten (W)-containing precursor, a hydrogen ( H₂ )-containing carrier gas, and a nitrogen-containing gas.

Description

Embodiments of this specification relate to methods used in the manufacture of electronic devices, and more particularly to a process for filling deep contact gaps in NAND devices with high-quality tungsten (W). Tungsten (W) is widely used in integrated circuit (IC) device manufacturing to form conductive features where relatively low electrical resistance and relatively high resistance to electromigration are desired. For example, tungsten may be used as a metal filler material for forming source contacts, drain contacts, metal gate fillers, gate contacts, interconnects (e.g., horizontal features formed on the surface of a dielectric material layer), and vias (e.g., vertical features formed through a dielectric material layer to connect other interconnect features located above and below the dielectric material layer). Due to its relatively low resistivity, tungsten is also commonly used to form M0 level interconnects in IC devices, as well as bit and word lines used to address individual memory cells within memory cell arrays in three-dimensional NAND (3D NAND) devices. In next-generation NAND devices, the metal contact structure will transition from a single-stage tapered structure to a multi-stage structure with landing pads. Conventional deposition processes, such as chemical vapor deposition (CVD), have shown that filling deep contact gaps, such as those in multi-stage structures with landing pads, with tungsten presents the challenge of void or seam formation in the filled tungsten. Therefore, a process is needed that can fill the deep contact gaps of NAND devices with tungsten (W) to form high-quality interconnects. Embodiments of this disclosure provide a method for filling a via having a necking point. The method includes the steps of: performing a pre-cleaning process to remove residue from the exposed surface of the metal layer at the bottom of the via and to restore the inner surface of the via, wherein the via is formed in a dielectric layer and has a necking point protruding into the via; performing a selective deposition process to partially fill the via with a metal filler material from the exposed surface of the metal layer below the necking point; performing a liner deposition process to form a liner layer on the exposed inner surface of the via; and performing a metal filling process to fill the via with a metal filler material. Embodiments of this disclosure provide a method for filling vias having a necking point. The method includes the steps of: performing a liner deposition process to form a liner layer on the exposed inner surface of a via, wherein the via is formed within a dielectric layer and has a necking point protruding into the via; performing a liner pullback process to remove the liner layer above the necking point; performing a selective deposition process to partially fill the via with a metal filler material from the exposed surface of the liner layer below the necking point; and performing a metal filling process to fill the via with the metal filler material. Embodiments of this disclosure provide a method for filling vias having a necking point. The method includes the steps of: performing a liner deposition process to form a liner layer on the exposed inner surface of a via, wherein the via is formed within a dielectric layer and has a necking point protruding into the via; performing a liner pullback process to remove the liner layer above the necking point; performing a selective deposition process to partially fill the via with a metal filler material from the exposed surface of the liner layer below the necking point; and performing a metal filling process to fill the via with the metal filler material. To enable a detailed understanding of the above-mentioned features of this disclosure, a more specific description of this disclosure, which is briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that since this disclosure may allow for other equally valid embodiments, the accompanying drawings only illustrate exemplary embodiments of this disclosure and should therefore not be considered to limit its scope. This is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure.This is a schematic diagram of an intermediate process (MEOL) portion of an exemplary semiconductor structure according to one or more embodiments of the present disclosure.This is a process flow diagram of a method for filling vias in a landing pad structure in a semiconductor structure according to a first embodiment of the present disclosure.This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 3.This is a partial cross-sectional view of a semiconductor structure corresponding to a certain state of the method shown in Figure 3.This is a partial cross-