JP-2026514372-A - Source/drain contact replacement method in complementary field-effect transistor (CFET) devices

Abstract

The semiconductor structure forming the complementary field-effect transistor (CFET) includes a metal gate, a bottom field-effect transistor (FET) module comprising a plurality of channel layers extending through the metal gate in a first direction, and bottom source/drain (S/D) contacts electrically connected to the plurality of channel layers via a bottom epitaxial (epi) S/D and a bottom interface, and an upper FET module stacked on the bottom FET module in a second direction orthogonal to the first direction, comprising a plurality of channel layers extending through the metal gate in the first direction, and upper source/drain (S/D) contacts electrically connected to the plurality of channel layers via an upper epitaxial (epi) S/D and an upper interface, wherein the bottom S/D contact and the upper S/D contact each contain cobalt (Co) or tungsten (W). [Selection Diagram] Figure 2A

Inventors

• パル， アシシュ
• バジージ， エル メディー
• プラナタルティハラン， バラスブラマニアン

Assignees

• アプライド マテリアルズ インコーポレイテッド

Dates

Publication Date

20260511

Application Date

20240304

Priority Date

20230331

Claims (20)

1. A semiconductor structure that forms a complementary field-effect transistor (CFET), Metal gate and This is a bottom field-effect transistor (FET) module, Multiple channel layers extending in a first direction through the metal gate, A bottom FET module including a bottom epitaxial (epi) S/D and bottom source/drain (S/D) contacts electrically connected to the plurality of channel layers via a bottom interface, An upper FET module stacked on the bottom FET module in a second direction perpendicular to the first direction, A plurality of channel layers extending in the first direction through the metal gate, An upper FET module includes an upper epitaxial (epi) S/D and upper source/drain (S/D) contacts electrically connected to the plurality of channel layers via an upper interface, The bottom S/D contact and the upper S/D contact each have a semiconductor structure containing cobalt (Co) or tungsten (W).
2. The semiconductor structure according to claim 1, wherein the metal gate comprises cobalt (Co) or tungsten (W).
3. The semiconductor structure according to claim 1, wherein the plurality of channel layers in the upper FET module and the plurality of channel layers in the bottom FET module each contain silicon.
4. The semiconductor structure according to claim 1, wherein the bottom epitaxial S/D is doped with p-type material, and the upper epitaxial S/D is doped with n-type material.
5. The semiconductor structure according to claim 1, wherein the bottom epitaxial S/D is doped with n-type, and the upper epitaxial S/D is doped with p-type.
6. The semiconductor structure according to claim 1, wherein the upper interface and the lower interface each contain a metal silicide.
7. A method for forming a complementary field-effect transistor (CFET), An upper cover spacer formation process is performed to deposit an upper cover spacer that covers the exposed surface of the upper nanosheet and a spacer around the upper nanosheet along a first plane perpendicular to the first direction, The upper nanosheet is laminated on the bottom nanosheet in a second direction perpendicular to the first direction. The upper nanosheet and the lower nanosheet each include a plurality of channel layers extending in the first direction through the dummy gate. Perform the upper cover spacer formation process, To form a bottom epi-S/D on the exposed surface of the bottom nanosheet along the first plane, a bottom epitaxial (epi) source/drain (S/D) formation process is performed, The process involves depositing a bottom interlayer insulator (ILD) on the spacer surface around the bottom epi S/D, patterning the bottom ILD to form a dummy contact, and then performing a bottom contact patterning and sacrificial filling process to remove the upper cover spacer. The process involves performing an upper epi S/D formation process to form an upper epi S/D on the exposed surface of the upper nanosheet along the first plane and to form an upper ILD around the upper epi S/D, In order to replace the dummy gate with a metal gate, a metal gate replacement (RMG) process is performed. To pattern the upper ILD and form the upper S/D contact, an upper contact patterning and metal filling process is performed. In order to selectively etch the dummy contact, a dummy contact stripping process is performed following the bottom epitaxial S/D formation process, the top epitaxial S/D formation process, and the RMG process. A method comprising performing a replacement bottom S/D contact formation process to form bottom S/D contacts in the portion etched in the dummy contact strip process.
8. The method according to claim 7, wherein the bottom S/D contact, the upper S/D contact, and the metal gate each contain cobalt (Co) or tungsten (W).
9. The method according to claim 7, wherein the dummy contact comprises silicon oxide ( SiO₂ ), silicon nitride ( Si₃N₄ ), silicon carbide (SiC), or a combination thereof.
10. The method according to claim 7, wherein the bottom ILD and the upper ILD each contain silicon oxide ( SiO₂ ).
11. The method according to claim 7, wherein the bottom epistatic S/D is doped with p-type, and the upper epistatic S/D is doped with n-type.
12. The method according to claim 11, further comprising performing an annealing process to activate the dopants in the bottom epi-S/D and the upper epi-S/D before the dummy contact strip process.
13. The method according to claim 7, wherein the bottom epitaxial S/D formation process and the upper epitaxial S/D formation process are carried out at a temperature of 400°C to 1200°C.
14. The method according to claim 7, wherein the RMG process is carried out at a temperature of 150°C to 950°C.
15. A semiconductor structure that forms a complementary field-effect transistor (CFET), Metal gate and This is a bottom field-effect transistor (FET) module, Multiple channel layers extending in a first direction through the metal gate, A bottom FET module including a bottom epitaxial (epi) S/D and dummy contacts connected to the plurality of channel layers via a bottom interface, An upper FET module stacked on the bottom FET module in a second direction perpendicular to the first direction, A plurality of channel layers extending in the first direction through the metal gate, An upper FET module includes an upper epitaxial (epi) S/D and upper source/drain (S/D) contacts electrically connected to the plurality of channel layers via an upper interface, The dummy contact comprises silicon oxide ( SiO₂ ), silicon nitride ( Si₃N₄ ), silicon carbide (SiC), or a combination thereof, and the upper S/D contact comprises cobalt (Co) or tungsten (W), thus forming a semiconductor structure.
16. The semiconductor structure according to claim 15, wherein the metal gate comprises cobalt (Co) or tungsten (W).
17. The semiconductor structure according to claim 15, wherein each of the plurality of channel layers in the upper FET module and the plurality of channel layers in the bottom FET module contains silicon.
18. The semiconductor structure according to claim 15, wherein the bottom epitaxial S/D is doped with p-type material, and the upper epitaxial S/D is doped with n-type material.
19. The semiconductor structure according to claim 15, wherein the bottom epitaxial S/D is doped with n-type material, and the upper epitaxial S/D is doped with p-type material.
20. The semiconductor structure according to claim 15, wherein the upper interface and the lower interface each contain a metal silicide.

Description

Cross-reference to related applications [0001] This application claims priority to U.S. Provisional Application No. 63/456,435 filed March 31, 2023, the contents of which are incorporated herein by reference in their entirety. [0002] The embodiments described herein generally relate to semiconductor device manufacturing, and more specifically to methods for forming complementary field-effect transistor (CFET) devices. [0003] To continue scaling beyond the physical limits of planar metal oxide semiconductor field-effect transistors (MOSFETs), three-dimensional FinFETs, multilayer nanosheet gate all-around FETs (GAA FETs), and complementary FETs (CFETs) have been proposed. In CFET architectures, n-devices and p-devices are stacked vertically on top of each other, eliminating the n-p spacing from the standard cell height. In currently proposed process flows, the contact trenches of the bottom device are filled with silicide and metal contact plugs before forming the top device. As a result, silicides and contact plugs formed from currently known materials such as titanium silicide, cobalt, or tungsten may not withstand the high-temperature process for forming the top device and may degrade during the high-temperature process. Using materials that can withstand such high-temperature processes may result in higher resistance and lead to increased complexity in the deposition and etching processes. [0004] Therefore, an improved method is needed for fabricating the silicide and metal contact plug in the bottom device of the CFET architecture. [0005] Embodiments of the present disclosure provide a semiconductor structure for forming a complementary field-effect transistor (CFET). The semiconductor structure includes a metal gate, a bottom field-effect transistor (FET) module comprising a plurality of channel layers extending through the metal gate in a first direction, and bottom source/drain (S/D) contacts electrically connected to the plurality of channel layers via a bottom epitaxial (epi) S/D and a bottom interface, and an upper FET module stacked on the bottom FET module in a second direction orthogonal to the first direction, comprising a plurality of channel layers extending through the metal gate in the first direction, and upper source/drain (S/D) contacts electrically connected to the plurality of channel layers via an upper epitaxial (epi) S/D and an upper interface, wherein the bottom S/D contacts and upper S/D contacts each comprise cobalt (Co) or tungsten (W). [0006] Embodiments of the present disclosure provide a method for forming a complementary field-effect transistor (CFET). The method comprises: performing an upper cover spacer formation process to deposit an upper cover spacer covering the exposed surface of an upper nanosheet and a spacer around the upper nanosheet along a first plane perpendicular to a first direction, wherein the upper nanosheet is laminated on a bottom nanosheet in a second direction perpendicular to the first direction, and the upper nanosheet and bottom nanosheet each include a plurality of channel layers extending in the first direction through a dummy gate; performing a bottom epitaxial (epi)source/drain (S/D) formation process to form a bottom epi S/D on the exposed surface of the bottom nanosheet along the first plane; and depositing a bottom interlayer insulator (ILD) on the spacer surface around the bottom epi S/D, patterning the bottom ILD, forming a dummy contact, and removing the upper cover spacer by performing a bottom contact process. The process includes performing a turning and sacrificial filling process; performing an upper epitaxial S/D formation process to form upper epitaxial S/Ds on the exposed surfaces of the upper nanosheets along a first plane and upper intralayer diodes (ILDs) around the upper epitaxial S/Ds; performing a metal gate replacement (RMG) process to replace dummy gates with metal gates; performing an upper contact patterning and metal filling process to pattern the upper ILDs and form upper S/D contacts; performing a dummy contact stripping process following the bottom epitaxial S/D formation process, the upper epitaxial S/D formation process, and the RMG process to selectively etch the dummy contacts; and performing a replacement bottom S/D contact formation process to form bottom S/D contacts in the portions etched by the dummy contact stripping process. [0007] Embodiments of the present disclosure provide a semiconductor structure for forming a complementary field-effect transistor (CFET). The semiconductor structure includes a metal gate and a bottom field-effect transistor (FET) module, the bottom FET module including a plurality of channel layers extending through the metal gate in a first direction and dummy contacts connected to the plurality of channel layers via a bottom epitaxial (epi) S/D and a bottom interface, and an upper FET module stacked on the bottom FET module in a second direction orthogonal to the first direction,