JP-2026514380-A - Device having a memory cell calibration mechanism and method for operating said device

Abstract

Methods, apparatuses, and systems for tracking charge loss are described. An apparatus may include a tracking mechanism configured to perform direct measurements for tracking charge loss in a first type of cell. An apparatus may be configured to designate a set of first type cells as a surrogate for modeling charge loss in a second type of cell having a different storage density than the first type of cell. The apparatus may perform measurements on the surrogate set of first type cells and use the tracking mechanism to translate the measurement results to respond to charge loss in the second type of cell.

Inventors

• テイ イー ヤン
• チャン レイ
• ケインツ スティーブ
• ゴー エドリック

Assignees

• マイクロン テクノロジー，インク．

Dates

Publication Date

20260511

Application Date

20240307

Priority Date

20230328

Claims (20)

1. A memory device, A memory array comprising non-temporary, rewritable memory cells grouped into blocks and configured to store charges representing stored data, A memory block is configured to include a second type of cell, which is specified to store a second number of bits per cell and is configured to store accessible data, and the memory block includes a word line configured as a first type of cell, which is specified to store a first number of bits per cell greater than the second number of bits and is configured as a surrogate for modeling charge loss in the second type of cell. The memory array and a logic circuit coupled to the memory array, Padding the first type of cell with a predetermined data value for monitoring charge loss over time, wherein the first type of memory cell is padded to represent the storage state of the second type of cell, Since it operates in the first type of cell described above, the measurement output is obtained directly, The process involves calculating a converted measurement result for the second type of cell using the measurement output and the conversion mechanism, The converted measurement results include an estimate of the charge loss in the second type of cell, and also, The conversion mechanism represents the relationship between the charge losses in the first type of cell and the second type of cell. The above calculation and, Extracting an access adjustment based on the converted measurement result, wherein the access adjustment is for adjusting the read level voltage to respond to the charge loss in the second type of cell in the read from the second type of cell, The logic circuit configured to do the following, The memory device, including the memory device.
2. A memory device according to claim 1, The memory device wherein the second type of cell is a triple-level cell (TLC) and the first type of cell is a quad-level cell (QLC).
3. A memory device according to claim 1, The memory device wherein the second type of cell has (1) a maximum storage capacity greater than the first number of bits, and (2) is dynamically configured to store less than the maximum capacity in order to reduce the write time compared to the first type of cell.
4. A memory device according to claim 1, The memory device is configured such that the logic circuit acquires the measurement output and calculates the converted measurement result during read error handling, media scanning, periodic scanning, or a combination thereof.
5. A memory device according to claim 1, The memory device wherein the logic circuit is configured to extract the access adjustment without (1) tracking the storage period in the second type of cell, (2) directly measuring the charge loss in the second type of cell, and (3) adjusting with respect to temperature, or a combination thereof.
6. A method for operating a memory device including a rewritable memory cell configured to store an electric charge representing stored data, Determining a first type of memory cell configured to have a first storage density, wherein the first type of memory cell is configured as a substitute for a second type of memory cell having a second storage density. Pad the first type of memory cell with a predetermined data value for monitoring charge loss over time, The method involves obtaining a measurement output directly from operating in the first type of cell, wherein the measurement output reflects the charge loss in the first type of cell, and the method of obtaining the measurement output is described above. The process involves calculating a converted measurement result based on the measurement output and the conversion mechanism, which maps the measured charge loss in the first type of cell to the estimated charge loss in the second type of cell, and extracting an access adjustment based on the converted measurement result, wherein the access adjustment is for adjusting the readout level voltage for the second type of cell. The method comprising the above.
7. The method according to claim 6, wherein the measurement output is obtained Gradually increasing the access group voltage in the first type of cell, The measurement output is determined as the access group voltage that produces a predetermined reaction with respect to the first type of cell, The method comprises calculating an adjusted access level based on combining the access adjustment with the converted measurement result, and reading the second type of cell using the adjusted access level.
8. The method according to claim 7, The first type of cell and the second type of cell include a memory block. The first type of cell is connected to a proxy word line, The first memory density is the maximum memory density for the memory block, The second type of cell is (1) connected to a separate memory word line, and (2) dynamically configured to store the second memory density less than the maximum memory density, Gradually increasing the access group voltage includes continuing to gradually increase the access group voltage during and after determining the measurement output and while calculating the converted measurement result, extracting the access adjustment, and calculating the adjusted access level. Reading the second type of cell described above is: The method comprising: gradually increasing the voltage on the memory word line simultaneously with the access group voltage; and raising the voltage on the memory word line to at least the adjusted access level.
9. The method according to claim 8, The maximum storage density for the memory block is 4 bits per cell. The method wherein the second type of cell is a QLC dynamically configured to operate as a TLC to reduce read and write times.
10. The method according to claim 7, Gradually increasing the access group voltage means The method comprising increasing the access group voltage to a minimum measurable value according to a first step size, and increasing the access group voltage beyond the minimum measurable value using a measurement step size having a smaller scale, a longer duration, or both, compared to the first step size.
11. A memory device, A rewritable memory cell comprising a first type of cell and a second type of cell, each designated to store a different number of bits, and configured to store charges representing stored data, grouped into blocks; and a logic circuit coupled to the rewritable memory cell, Determine a proxy access group which includes a set of the first type of cells configured to model the charge loss for the second type of cell, The surrogate access group is padded to establish an initial state for tracking the charge level in the second type of cell, Based on directly obtaining a measurement output representing the charge loss over time from the initial state from the proxy access group, and using the measurement output to convert the measurement output to represent the estimated charge loss in the second type of cell, access adjustments for reading the second type of cell are extracted. The logic circuit configured as described above, A memory device that includes the following.
12. A memory device according to claim 11, The aforementioned rewritable memory cell is a flash memory cell. The second type of cell is a triple-level cell (TLC), and also, The memory device wherein the first type of cell is a quad-level cell (QLC).
13. A memory device according to claim 11, The memory device wherein the second type of cell has (1) a maximum storage capacity greater than the first number of bits, and (2) is configured to store less than the maximum capacity in order to reduce the write time.
14. A memory device according to claim 13, The second type of cell includes a memory block and is dynamically configured to store less than the maximum capacity, The memory device wherein the proxy access group is a word line in the memory block configured to operate as a cell of the first type.
15. A memory device according to claim 11, The memory device wherein the logic circuit is configured to extract the access adjustment instead of (1) tracking the storage period in the second type of cell, (2) directly measuring the charge loss in the second type of cell, or (3) making adjustments with respect to temperature, or a combination thereof.
16. A memory device according to claim 11, The memory device is configured such that the logic circuit acquires the measurement output and calculates the converted measurement result during readout error handling, media scanning, periodic scanning, or a combination thereof.
17. A memory device according to claim 11, The aforementioned logic circuit is The access group voltage for the aforementioned proxy access group is gradually increased. The measurement output is determined as the access group voltage that produces a predetermined reaction with respect to the first type of cell. The converted measurement result is calculated based on the measurement output and the conversion mechanism, and the measured charge loss in the first type of cell is mapped to the estimated charge loss in the second type of cell. Based on the converted measurement results, the access adjustment is extracted, The adjusted access level is calculated based on the combination of the access adjustment with the converted measurement result, and the second type of cell is read using the adjusted access level. The memory device configured as described above.
18. A memory device according to claim 17, The first type of cell and the second type of cell include a memory block. The proxy access group includes the first type of cell connected to the proxy word line, The first memory density is the maximum memory density for the memory block, The second type of cell is (1) connected to a separate memory word line, and (2) dynamically configured to store the second memory density less than the maximum memory density, The aforementioned logic circuit further, During and after determining the measurement output, in parallel with (1) calculating the converted measurement result, (2) extracting the access adjustment, and calculating the adjusted access level, the access group voltage is continuously increased. The voltage is gradually increased on the memory word line that matches the access group voltage, Based on raising the voltage on the memory word line to at least the adjusted access level, The memory device configured to read out the second type of cell.
19. A memory device according to claim 18, The maximum storage density for the memory block is 4 bits per cell. The memory device wherein the second type of cell is a QLC dynamically configured to store three bits or less per cell in order to reduce read and write times.
20. A memory device according to claim 17, The aforementioned logic further, Increasing the access group voltage to a minimum measurable value according to the first step size, and increasing the access group voltage beyond the minimum measurable value using a measurement step size having a smaller scale, a longer duration, or both, compared to the first step size. The memory device is configured to gradually increase the access group voltage based on the following.

Description

The disclosed embodiments relate to an apparatus, and more particularly to a semiconductor memory apparatus having a memory cell calibration mechanism, and a method for operating the apparatus. A memory system may employ memory devices for storing and accessing information. Memory devices may include volatile memory devices, non-volatile memory devices (e.g., flash memory using "NAND" technology or logic gates, flash memory using "NOR" technology or logic gates, or a combination thereof), or combination devices. Memory devices utilize electrical energy at corresponding threshold levels or processing/read voltage levels to store and access data. However, the performance or characteristics of memory devices change or deteriorate over time, with use, and environmental conditions. This change in performance or characteristics can become inconsistent with the threshold or processing voltage levels over time, leading to errors and other performance problems. The altered performance further deteriorates as the density of the memory device increases (e.g., by storing more bits per cell). The aforementioned and other purposes, features and advantages of this disclosure will become clear from the following description of embodiments as illustrated in the accompanying drawings, where the same reference numerals refer to the same parts among the various figures. The figures are not necessarily to a constant scale, but rather to an emphasis used to illustrate the principles of this disclosure. This is a block diagram of the calculation system according to an embodiment of this technology. This is an illustration of charge loss. This is an illustration of charge loss. This is an example of a conversion mechanism according to an embodiment of this technology. This is an illustration of memory state measurement according to an embodiment of this technology. This flowchart illustrates an exemplary method for manufacturing and operating an apparatus according to an embodiment of this technology. This is a schematic diagram of a system including the apparatus according to an embodiment of this technology. As detailed below, the technology disclosed herein relates to an apparatus for calibrating memory cells in devices comprising multiple types of cells, such as memory systems, systems having memory devices, associated methods, and others. The apparatus is capable of tracking or measuring the amount of charge loss for a first type of memory cell (e.g., higher-density memory cells such as quad-level cells (QLCs)), and the resulting charge loss can be used to estimate the charge loss for a second type of memory cell (e.g., lower-density memory cells such as triple-level cells (TLCs), multi-level cells (MLCs), and/or single-level cells (SLCs)). Technological advancements have made it possible for memory cells (e.g., NAND flash memory cells) to store an increasing number of bits. The storage capacity of a memory cell can be expressed as bits per cell (BPC). For example, SLC may have a capacity of 1 BPC, MLC 2 BPC, TLC 3 BPC, and QLC 4 BPC. Increasing the BPC allows more bits to be stored on a single wafer, thus reducing the cost per bit for a given die size. Furthermore, including multiple cells of different types or densities within a group of cells/each group or within a single device can provide additional features and operational flexibility. For example, during higher demand loads or relatively frequent memory access, a device can utilize lower-density cells for temporary storage similar to cache memory. In such write surges, the device can utilize the faster write speed of lower-density cells to initially receive the data. Next, the device can move the initially received data to higher-density cells (for example, 12 bits stored in 12 SLCs to 4 TLCs or 3 QLCs). However, different types of memory cells can behave differently. For example, QLC and TLC may have different charge loss patterns. That is, different types of memory cells may be exposed to different rates of charge loss. Conventional methods for measuring charge loss required separate measurement circuits. Other conventional methods for tracking and calculating charge loss require relatively large tables used to track write time and/or storage duration for each cell or group of cells. Therefore, such conventional methods require additional resources, such as dedicated measurement circuits or designated storage space, for each type of memory to track the tables. Embodiments of the technology described herein may utilize resources for one type of memory cell (e.g., QLC) to calculate/track estimated charge loss for another type of memory cell (e.g., faster, lower-density cells such as TLC). For example, the apparatus may include circuitry and/or routines for measuring the charge loss characteristics of one or more QLC blocks. The apparatus may include or select one or more dummy word lines (WLs) of QLC as surrogates to represent and track the charge loss behavior of one