JP-2026514411-A - Method for etching high aspect ratio structures

Abstract

This specification discloses a method and system for etching high aspect ratio structures in a semiconductor processing chamber. In one embodiment, a method for patterning a substrate includes etching the substrate to form recesses, depositing a passivation layer on the sidewalls of the recesses, processing the passivation layer, and etching the recesses to a second depth. The substrate etching forms recesses to a first depth, on which a mask layer is placed. The processing of the passivation layer is for removing occluding material formed from etching byproducts on the mask layer. The recesses are etched to a second depth while maintaining minimal variation in the recess sidewall width. [Selection Diagram] Figure 2

Inventors

• チアオ， フォン
• チョウ， ハイロン
• フー， チーアン
• パーク， サンジュン
• チェ， ジャヨン
• アガーウォール， ラデ
• リウ， トン

Assignees

• アプライド マテリアルズ インコーポレイテッド

Dates

Publication Date

20260511

Application Date

20240112

Priority Date

20230330

Claims (20)

1. A method for patterning a circuit board, (a) Etching the substrate to form a recess to a first depth, wherein a mask layer is placed on the substrate, (b) Depositing a passivation layer on the side wall of the recess, (c) To remove the blockage material formed from etching by-products on the mask layer, the passivation layer is treated, (d) Etching the recess to a second depth while maintaining the minimum variation in the width of the recess side wall, Methods that include...
2. The method according to claim 1, wherein the first depth is approximately 2 nanometers to approximately 300 nanometers.
3. The method according to claim 2, wherein the first depth is approximately 200 nanometers.
4. The method according to claim 1, wherein the deposition of the passivation layer includes exposing the substrate to a plasma formed from an oxygen-containing precursor gas.
5. The method according to claim 1, further comprising depositing the passivation layer to generate an oxygen plasma at approximately 13.56 MHz with an RF power of approximately 2,500 W and a bias power of approximately 100 W.
6. The method according to claim 1, wherein processing the passivation layer includes exposing the sidewalls of the mask layer.
7. The method according to claim 1, wherein the substrate includes a plurality of silicon layers, or alternating layers of silicon and silicon germanium.
8. The method according to claim 1, further comprising processing the passivation layer to generate a plasma from a mixed gas of NF3 , Ar, and O2 under a pressure of about 20 millitorl to about 60 millitorl.
9. The method according to claim 8, further comprising treating the passivation layer by exposing the substrate for a duration of approximately 10 to 100 seconds.
10. The method according to claim 1, further comprising generating a plasma from a mixed gas containing Cl₂ , HBr, and O₂ in etching the substrate.
11. The method according to claim 10, wherein plasma generation uses a bias power of 4,000 watts to approximately 4,500 watts.
12. The method according to claim 1, further comprising generating a plasma from a mixed gas containing Cl₂ , HBr, and O₂ in etching the recess.
13. The method according to claim 12, wherein plasma generation uses a bias power of 4,000 watts to approximately 4,500 watts.
14. The method according to claim 1, wherein (a), (b), (c), and (d) are repeated until the recess has an aspect ratio of at least 100:1.
15. The method according to claim 1, wherein maintaining a minimum variation in the width of the recessed side wall includes keeping the variation within approximately 10 nanometers.
16. A method for patterning a circuit board, (a) Etching the substrate in order to remove the oxide layer and expose the silicon-containing film laminate, (b) Etching the substrate to form a recess to a first depth within the film stack, wherein the substrate comprises a mask layer disposed on the film stack, the mask layer has an inner wall, the film stack is disposed on the substrate, and etching the substrate is Generating a plasma from a mixed gas of Cl₂ , HBr, O₂ , and Ar, Etching the substrate to form recesses to a first depth, including exposing the substrate to the plasma for about 10 seconds to about 200 seconds, (c) Exposing the substrate to the generated oxygen plasma for about 10 to 20 seconds to oxidize the side walls of the recesses and the inner walls of the mask layer having silicon-containing etching byproducts, (d) Exposing the sidewalls of the mask layer by controlled etching, wherein the controlled etching is Generating a plasma from a mixed gas of NF3 , Ar, and O2 , The substrate is exposed to the plasma for approximately 10 to 200 seconds. (e) Repeat (b), (c), (d), (f) Etching the recess to a second depth while maintaining the vertical profile of the first depth within 5 nanometers from the center of the recess, Methods that include...
17. The method according to claim 16, wherein the final depth has a 100:1 aspect ratio structure.
18. A system for processing semiconductor substrates, A chamber comprising a lid, a main body, side walls, and a substrate support, The processing space defined by the lid, the body, and the side wall, A system controller connected to the aforementioned chamber, The system controller has a non-temporary computer-readable medium in which instructions are stored, and when an instruction is executed by the processor, it is sent to the process. (a) Etching the substrate in order to remove the thin layer of oxide and expose the silicon-containing film stack, (b) Etching the substrate to form a recess to a first depth, wherein a mask layer is placed on the substrate, (c) Depositing a passivation layer on the side wall of the recess, (d) To remove the blockage material formed from etching by-products on the mask layer, the passivation layer is treated, (e) Etching the recess to a second depth while maintaining the minimum variation in the width of the recess side wall, The process is to execute the following steps. system.
19. The system according to claim 18, further comprising a final depth having an aspect ratio of at least 100:1.
20. The system according to claim 19, wherein the final depth includes a recess sidewall width profile of approximately 10 nanometers or less.

Description

[0001] Embodiments of this disclosure generally relate to semiconductor etching methods and systems. More specifically, embodiments of this disclosure relate to etching methods for fabricating high aspect ratio device structures. Description of Related Technologies [0002] In semiconductor manufacturing, integrated circuits (ICs) are formed on semiconductor substrates through various manufacturing steps, including etching. Conventional etching processes used in film stack etching utilize a single etching process to achieve deep structures. These processes can be repeated to achieve the desired depth at the expense of the desired vertical shape. These undesirable vertical profiles can lead to reduced device performance or device failure. Therefore, there is a need for improved methods to etch high aspect ratio structures with desired vertical profiles. [0003] This specification discloses methods and systems for etching high aspect ratio structures in a semiconductor processing chamber. In one embodiment, a method for patterning a substrate includes etching the substrate to form recesses, depositing a passivation layer on the sidewalls of the recesses, processing the passivation layer, and etching the recesses to a second depth. The substrate etching forms recesses to a first depth, with a mask layer positioned on the substrate. Processing the passivation layer is for removing occluding material formed from etching byproducts on the mask layer. The method includes etching the recesses to a second depth while maintaining a minimum variation in the recess sidewall width. [0004] In another embodiment, a method for patterning a substrate includes etching the substrate to remove a thin layer of oxide and expose a silicon-containing film stack; etching the substrate to form recesses in the film stack to a first depth; oxidizing the sidewalls of the recesses and the inner walls of the mask layer; exposing the sidewalls of the mask layer by controlled etching; and repeating the process to etch the recesses to a final depth while maintaining a vertical profile. The substrate comprises a mask layer placed on top of the film stack, the mask layer having an inner wall, the film stack is placed on the substrate, and etching the substrate includes generating a plasma from a mixed gas of Cl₂ , HBr, O₂ , and Ar, and exposing the substrate to the plasma for about 10 to about 200 seconds. The method includes oxidizing the sidewalls of the recesses and the inner walls of the mask layer by exposing the substrate to the generated oxygen plasma for about 10 to about 20 seconds, the inner walls of the mask layer having silicon-containing etching byproducts. The method includes exposing the sidewalls of a mask layer by controlled etching, the controlled etching including generating a plasma from a mixed gas of NF3 , Ar, and O2 , and exposing the substrate to the plasma for about 10 to 200 seconds. The method includes etching a recess to a final depth while maintaining a vertical profile of a first depth within 5 nanometers from the center of the recess, and etching the recess to a second depth. [0005] In yet another embodiment, a system for processing a semiconductor substrate comprises a chamber and a system controller. The chamber comprises a lid, a body, side walls, and a substrate support. The processing space is defined by the lid, body, and side walls of the chamber. The system controller is connected to the chamber and has a non-temporary computer-readable medium in which instructions are stored. When these instructions are executed by the processor, the system controller causes the process to perform the following steps: (a) etching the substrate to remove a thin layer of oxide and expose a silicon-containing film stack; (b) etching the substrate to form a recess to a first depth; (c) etching the substrate on which the mask layer is placed; (d) processing the passivation layer to remove occluding material formed from etching byproducts on the mask layer; and (e) etching the recess to a second depth while maintaining a minimum variation in the recess side wall width. [0006] In another embodiment, instructions are stored in a non-temporary computer-readable medium, and when executed by a processor, the instructions cause a process to perform the steps of the apparatus and/or method described above. [0007] To enable a more detailed understanding of the features of this disclosure described above, a more detailed description of this disclosure, which is briefly summarized above, can be obtained by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be considered to limit the scope of this disclosure, and other equally valid embodiments are permitted. [0008] This is a schematic side cross-sectional view of one or more plasma processing systems according to the method described herein.[0009] This is