JP-2026514425-A - Direct connection on buried power rails

Abstract

An integrated circuit comprising a plurality of transistors and a method for manufacturing the same, wherein each transistor comprises a source, a drain, and a channel located between the source and the drain. The integrated circuit also comprises a plurality of buried power rails comprising a plurality of VSS power rails and a plurality of VDD power rails, at least one VSS pad and at least one VDD pad, a plurality of vias electrically connecting at least one VSS pad to at least two of the plurality of VSS power rails, and a plurality of vias electrically connecting at least one VDD pad to at least two of the plurality of buried VDD power rails. [Selection Diagram] Figure 1

Inventors

• カトカール ラジェッシュ
• ハーバ ベルガセム

Assignees

• アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド

Dates

Publication Date

20260511

Application Date

20240329

Priority Date

20230630

Claims (20)

1. It is an integrated circuit, Multiple transistors located on the first side of the substrate, A plurality of buried power rails connected to the plurality of transistors, comprising a plurality of VSS power rails and a plurality of VDD power rails, At least one VSS pad and at least one VDD pad, A plurality of vias electrically connecting the at least one VSS pad to at least two of the plurality of VSS power rails, wherein the at least one VSS pad is located on the second side of the substrate opposite to the first side, The at least one VDD pad is electrically connected to at least two of the embedded plurality of VDD power rails by a plurality of vias, wherein the at least one VDD pad is located on the second side of the substrate opposite to the first side, An integrated circuit equipped with the following features.
2. The integrated circuit according to claim 1, wherein the plurality of VSS and VDD pads are provided on the back surface of the die.
3. The integrated circuit according to claim 1, wherein the plurality of VSS and VDD pads are configured for hybrid bonding.
4. The integrated circuit according to claim 1, wherein multiple buried VSS power rails or multiple buried VDD power rails supply power to multiple transistors.
5. The integrated circuit according to claim 1, wherein the plurality of buried power rails are arranged at the front end of line (FEOL).
6. The integrated circuit according to claim 1, wherein the at least one VSS pad and/or the at least one VDD pad has a length-to-width ratio in the range of 1:1 to 10:1.
7. The integrated circuit according to claim 1, wherein the plurality of transistors are Finn field-effect transistors (FinFETs) or gate-all-around field-effect transistors (GAAs).
8. The integrated circuit according to claim 1, further comprising a ground plane or reference plane located below the plurality of buried power rails.
9. The integrated circuit according to claim 1, wherein the at least one VSS pad and the at least one VDD pad are located 100 nm to 3 μm below the plurality of buried power rails.
10. The integrated circuit according to claim 8, wherein the ground plane or the reference plane is located 100 nm to 3 μm below the plurality of buried power rails.
11. The integrated circuit according to claim 8, wherein at least one of the length, width, and thickness of the at least one VSS pad differs from the length, width, and thickness of the at least one VDD pad.
12. The integrated circuit according to claim 8, wherein multiple vias include VSS vias and VDD vias, and all of the VSS vias are short-circuited to the ground plane or reference plane.
13. The integrated circuit according to claim 8, wherein the ground plane or the reference plane includes an opening that allows the VDD via to pass through the ground plane or the reference plane without being short-circuited to the ground plane or the reference plane.
14. The integrated circuit according to claim 8, wherein the ground plane or the reference plane is directly located on the at least one VSS pad.
15. The integrated circuit according to claim 8, wherein the ground plane or the reference plane is electrically connected to the at least one VSS pad by vias.
16. It is an integrated circuit, Multiple transistors located on the first side of the substrate, A plurality of buried power rails connected to the plurality of transistors, comprising a plurality of VSS power rails and a plurality of VDD power rails, Located on the second side of the substrate opposite to the first side, at least one VSS pad and at least one VDD pad, A power distribution network element hybrid-bonded to a hybrid bonding surface including the at least one VSS pad and the at least one VDD pad, An integrated circuit equipped with the following features.
17. The at least one VSS pad is electrically connected to at least two of the plurality of VSS power rails via a plurality of vias, The at least one VDD pad is electrically connected to at least two of the embedded plurality of VDD power rails via a plurality of vias, The integrated circuit according to claim 16, further comprising the above.
18. A method for manufacturing an integrated circuit having a back-side power supply, The first substrate is provided on its front surface, having a plurality of transistors, a plurality of embedded power rails, and a plurality of signal lines. The back surface of the first substrate is made thinner, To form multiple vias from the back surface of the first substrate to the multiple embedded power rails, Forming a bond pad on the back surface of the first substrate, wherein the bond pad is in electrical contact with each of the at least two embedded power rails via the plurality of vias, Methods that include...
19. The method according to claim 18, further comprising bonding a carrier to the front surface of the first substrate before thinning the back surface of the first substrate.
20. The method according to claim 18, further comprising hybrid bonding a second substrate having a power supply network formed inside to the back surface of the first substrate.

Description

(Cross-reference with related applications) This application claims priority to U.S. Patent Applications No. 18/345,607 and No. 18/345,581, which in turn claim the benefit of U.S. Provisional Application No. 63/456,453, filed on March 31, 2023, the contents of which are incorporated herein by reference in their entirety. This field relates to integrated circuit dies with embedded power rails. Conventional integrated circuits are fabricated using only the front surface of a semiconductor wafer. In the first part of the fabrication process, individual components (e.g., transistors, resistors, capacitors) are formed on the front surface. This first device section is called the front-end of line (FEOL). After the FEOL is complete, the second part of the integrated circuit, the back-end of line (BEOL), is fabricated on top of the FEOL on the front surface of the wafer. The BEOL consists of a stack of alternating dielectric and metallization layers, where interconnects and vias are formed. The interconnects include power lines that supply power to and from the devices, and signal lines used to obtain data from the devices. Signal lines are sometimes broadly referred to as signal distribution networks (SDNs), and power lines as power distribution networks (PDNs). The BEOL also includes pads for bonding the chip to a package or circuit board. As electrical components, particularly transistors, have become smaller and their number per chip has increased, the amount of wiring has increased proportionally, yet the chip size has remained relatively constant. While the size of interconnects at the transistor device level has decreased proportionally, the total number of metallization layers has increased significantly to accommodate the increase in interconnects at the chip level. These interconnect layers are connected to each other and to devices by increasingly smaller vias, particularly near the device level. However, the resistance of interconnects and vias increases as the via size decreases. As a result, resistance increases exponentially as interconnects and vias shrink to less than 10 nm. Furthermore, as the number of interconnects increases, the total ohmic drop from the upper metallization layer to the device gradually worsens. This ohmic drop also contributes to the Joule heating of the wiring layer, effectively increasing the operating temperature of the chip. This increase in resistance, ohmic drop due to resist, and increased chip temperature cast a shadow over the advantages of miniaturizing various electrical components. Therefore, it would be desirable and useful to provide a structure and method for manufacturing an integrated circuit to address this problem. Next, specific embodiments will be described with reference to the following drawings, but these are provided as examples only and are not limiting. Strength Specification No. 9,564,414Strength Patent No. 9,391,143U.S. Patent No. 10,434,749U.S. Patent No. 9,716,033U.S. Patent No. 9,852,988Strength Patent No. 11,195,748 This is a cross-sectional view of a conventional integrated circuit. This is a cross-sectional view of an integrated circuit having an embedded power rail. Figure 2A is a top view of the integrated circuit shown. This is a cross-sectional view of an integrated circuit according to several embodiments of the disclosed technology. Figure 2A is a top view of the integrated circuit shown. This is a cross-sectional view of an integrated circuit according to several embodiments of the disclosed technology. Figure 2A is a top view of the integrated circuit shown. Figures 4A and 4B are cross-sectional views of modified versions of the integrated circuit shown. Figures 4A and 4B show cross-sectional views of another modified example of the integrated circuit. This is a cross-sectional view showing a method for manufacturing an integrated circuit according to several embodiments of the disclosed technology.This is a cross-sectional view showing a method for manufacturing an integrated circuit according to several embodiments of the disclosed technology.This is a cross-sectional view showing a method for manufacturing an integrated circuit according to several embodiments of the disclosed technology.This is a cross-sectional view showing a method for manufacturing an integrated circuit according to several embodiments of the disclosed technology.This is a cross-sectional view showing a method for manufacturing an integrated circuit according to several embodiments of the disclosed technology.This is a cross-sectional view showing a method for manufacturing an integrated circuit according to several embodiments of the disclosed technology.This is a cross-sectional view showing a method for manufacturing an integrated circuit according to several embodiments of the disclosed technology.This is a cross-sectional view showing a method for manufacturing an integrated circuit according to several embodiments of the disclosed technology. This is a c