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JP-2026514505-A - Semiconductor devices having selectively doped gate electrode structures

JP2026514505AJP 2026514505 AJP2026514505 AJP 2026514505AJP-2026514505-A

Abstract

A semiconductor device is described that includes a selectively doped gate electrode. The semiconductor device includes a substrate (103) having a body region and a drift region (126), and a gate dielectric layer (134) on the substrate (103), the gate dielectric layer (134) extending over the body region and the drift region (126), and the gate dielectric layer (134) on the drift region (126), wherein a field reduction dielectric layer (120) is in lateral contact with the gate dielectric layer (134) at a certain position in the drift region (126). The semiconductor device also includes a gate electrode (142) having an n-doped first portion (164), a p-doped second portion (165), and an n-doped third portion (166). The selectively doped second portion (165) of the gate electrode (142) is located on the intersection (167) between the gate dielectric layer (134) and the field reduction dielectric layer (120).

Inventors

  • ダノープ ヴァルゲーゼ
  • ヘンリー リッツマン エドワーズ
  • ピンハイ ハオ

Assignees

  • テキサス インスツルメンツ インコーポレイテッド

Dates

Publication Date
20260511
Application Date
20240321
Priority Date
20230429

Claims (20)

  1. It is a semiconductor device, A substrate including a body region having a first conductivity type and a drift region having a second conductivity type opposite to the first conductivity type, The gate dielectric layer on the substrate, the gate dielectric layer extending over the body region and the drift region, The electric field reducing dielectric layer on the drift region, wherein the electric field reducing dielectric layer abuts laterally against the gate dielectric layer at a certain position in the drift region, The gate electrode on the gate dielectric layer and the field-reducing dielectric layer, wherein the gate electrode is A first portion having the second conductivity type, the first portion extending over the body region and the first portion of the drift region, A second portion having the first conductivity type and in contact with the first portion, the second portion extending over the second portion of the drift region and the first portion of the field-reducing dielectric layer, A third portion having the second conductivity type and in contact with the second portion, the third portion extending on the second portion of the field-reducing dielectric layer, The aforementioned shutdown terminal, Displaced in the body region and having the second conductivity type, A drain region having the second conductivity type is arranged in the drift region, Semiconductor devices, including those mentioned above.
  2. A semiconductor device according to claim 1, wherein the center of the second portion of the gate electrode substantially corresponds to the position in the drift region, and the center is located between the first portion of the gate electrode and the third portion of the gate electrode.
  3. A semiconductor device according to claim 1, wherein the width of the second portion of the gate electrode is at least twice the thickness of the gate electrode, and the width corresponds to the distance between the first portion and the third portion of the gate electrode.
  4. A semiconductor device according to claim 1, wherein the width of the second portion of the gate electrode is greater than 300 nanometers, and the width corresponds to the distance between the first portion and the third portion of the gate electrode.
  5. A semiconductor device according to claim 1, wherein the second portion of the gate electrode is degenerately doped or has an active average dopant density greater than 1 × 10¹⁹ / cm³ .
  6. A semiconductor device according to claim 1, wherein the field-reducing dielectric layer comprises silicon dioxide in a localized silicon oxidation (LOCOS) layer, or a dielectric material in a shallow trench isolation (STI) layer.
  7. A semiconductor device according to claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.
  8. A semiconductor device according to claim 1, wherein the gate electrode has a racetrack layout.
  9. A semiconductor device according to claim 1, The gate dielectric layer has a first thickness, The electric field reducing dielectric layer has a second thickness that is greater than the first thickness. Semiconductor devices.
  10. A semiconductor device according to claim 1, The source region has a first average dopant density that is greater than the second average dopant density of the body region. The drain region has a first average dopant density that is greater than the fourth average dopant density of the drift region. Semiconductor devices.
  11. A semiconductor device according to claim 1, A back gate region disposed in the body region and having the first conductivity type, the back gate region being electrically insulated and separated from the source region, Semiconductor devices, which further include the following.
  12. A semiconductor device according to claim 11, wherein the back gate region and the second portion of the gate electrode are formed simultaneously.
  13. It is a method, The method involves forming a body region and a drift region within a substrate, wherein the body region has a first conductivity type, and the drift region has a second conductivity type opposite to the first conductivity type. The process involves forming a gate dielectric layer on the substrate, wherein the gate dielectric layer extends over the body region and the drift region. Forming an electric field reducing dielectric layer on the drift region, wherein the electric field reducing dielectric layer is in lateral contact with the gate dielectric layer at a certain position in the drift region. Forming a gate electrode on the gate dielectric layer and the field-reducing dielectric layer, wherein the gate electrode is A first portion having the second conductivity type, the first portion extending over the body region and the first portion of the drift region, A second portion having the first conductivity type, in contact with the first portion, and extending over the second portion of the drift region and the first portion of the field-reducing dielectric layer, A third portion having the second conductivity type, in contact with the second portion, and extending over the second portion of the field-reducing dielectric layer, Forming the gate electrode including, The source region having the second conductivity type is formed within the body region, The drain region having the second conductivity type is formed within the drift region, Methods that include...
  14. A method according to claim 13, wherein the center of the second portion substantially corresponds to the position in the drift region, and the center is located between the first portion and the third portion of the gate electrode.
  15. A method according to claim 13, wherein the width of the second portion of the gate electrode is at least twice the thickness of the gate electrode, and the width corresponds to the distance between the first portion and the third portion of the gate electrode.
  16. A method according to claim 13, wherein the width of the second portion of the gate electrode is greater than 300 nanometers, and the width corresponds to the distance between the first portion and the third portion of the gate electrode.
  17. A method according to claim 13, wherein the second portion of the gate electrode is degenerately doped or has an active average dopant density greater than 1 × 10¹⁹ / cm³ .
  18. The method according to claim 13, The further includes forming a back gate region in the body region, wherein the back gate region has the first conductivity type, and the back gate region is electrically insulated and separated from the source region. method.
  19. A method according to claim 18, wherein forming the back gate region includes forming the second portion of the gate electrode.
  20. It is a semiconductor device, A substrate including a p-type body region and an n-type drift region, A first dielectric layer on the substrate, the first dielectric layer extending over the p-type body region and the n-type drift region, A second dielectric layer on the n-type drift region, which is thicker than the first dielectric layer and contacts the first dielectric layer laterally at a certain position in the n-type drift region, A gate electrode on the first dielectric layer and the second dielectric layer, wherein the gate electrode is An n-type first portion extending over the p-type body region and the first portion of the n-type drift region, A second portion of the p type abuts against the first portion of the n type and extends over the second portion of the n type drift region and the first portion of the second dielectric layer, A third n-type portion abuts against the second p-type portion and extends over the second portion of the second dielectric layer, The aforementioned shutdown terminal, An n-type source region is arranged in the aforementioned p-type body region, An n-type drain region is arranged in the aforementioned n-type drift region, Semiconductor devices, including those mentioned above.

Description

This description relates to the field of microelectronic devices. More specifically, this description relates to, but is not limited to, semiconductor devices having selectively doped gate electrode structures. Semiconductor components are constantly being improved to operate reliably with smaller feature sizes. Manufacturing semiconductor devices with increasingly higher performance while meeting reliability specifications is becoming increasingly challenging. This summary is provided to present a simplified version of some of the concepts described below, which are further described in the detailed description, including the attached drawings. This summary is not intended to limit the scope of the claimed subject matter. The examples described include semiconductor devices having selectively doped gate electrode structures. The semiconductor device includes a substrate having a body region having a first conductivity type and a drift region having a second conductivity type opposite to the first conductivity type; a gate dielectric layer on the substrate, extending over the body region and the drift region; an electric field reduction dielectric layer on the drift region, in lateral contact with the gate dielectric layer at a certain position in the drift region; a gate electrode on the gate dielectric layer and the electric field reduction dielectric layer, having a second conductivity type and having a first portion extending over the body region and a first portion of the drift region; a second portion having a first conductivity type, in contact with the first portion, and extending over a second portion of the drift region and a first portion of the electric field reduction dielectric layer; and a third portion having a second conductivity type, in contact with the second portion, and extending over a second portion of the electric field reduction dielectric layer. Furthermore, the semiconductor device includes a source region located in the body region and having a second conductivity type, and a drain region located in the drift region and having a second conductivity type. This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor having selectively doped gate electrode structures at various stages of formation. This is a top view of an exemplary microelectronic device, including selectively doped transistors. This is a cross-section of an alternative, exemplary microelectronic device, including a transistor with selectively doped gate electrodes. This graph shows time-dependent dielectric breakdown (TDDB) reliability data from transistors with uniformly doped gate electrode structures and transistors with selectively doped gate electrode structures. This description will be explained with reference to the attached drawings. The drawings are not drawn to a specific scale and are provided solely for illustrative purposes. Several aspects of this description will be described hereafter, with reference to illustrative application examples. Please understand that many specific details, relationships, and methods are presented for the purpose of understanding this description. Because some actions may occur in different orders and/or simultaneously with other actions or events, this description is not limited by the order in which such actions or events are described. Furthermore, not all actions or events describe