JP-2026514506-A - Semiconductor device with low concentration, opposite-type doping drain-end gate electrode

Abstract

Examples of disclosed devices include, for example, a microelectronic device (100) having a source region (138) and a drain region (139) extending into a semiconductor substrate (103), such as an integrated circuit, wherein the semiconductor substrate (103) has a second conductivity type, and the source region (138) and drain region (139) have opposite first conductivity types. A channel region having the second conductivity type extends between the source region (138) and the drain region (139). A gate electrode (128) on the channel region has a first portion (158) and a second portion (150). The first portion (158) has the second conductivity type and a first dopant concentration. The second portion (150) extends from the first portion toward the source region and has the second conductivity type and a second, even higher dopant concentration.

Inventors

• ヘンリー リッツマン エドワーズ

Assignees

• テキサス インスツルメンツ インコーポレイテッド

Dates

Publication Date

20260511

Application Date

20231229

Priority Date

20230831

Claims (20)

1. A microelectronic device, A source region and a drain region extending within a semiconductor substrate, wherein the semiconductor substrate has a second conductivity type, and the source region and the drain region have a first conductivity type opposite thereto, A channel region having the second conductivity type extending between the source region and the drain region, A gate electrode having a first portion and a second portion on the channel region, wherein the first portion has the second conductivity type and a first dopant concentration, and the second portion extends from the first portion toward the source region, and the second portion has the second conductivity type and a second, even higher dopant concentration, Microelectronic devices, including those mentioned above.
2. A microelectronic device according to claim 1, further comprising, below the first portion, a drain drift region of the first conductivity type extending from the drain region toward the source region, wherein the drain drift region has an average dopant concentration lower than the average dopant concentration of the drain region.
3. A microelectronic device according to claim 2, further comprising a field relaxation dielectric layer on the drain drift region, wherein the field relaxation dielectric layer extends from a gate dielectric layer located beneath the first portion of the gate electrode, and the field relaxation dielectric layer has a thickness greater than the thickness of the gate dielectric layer.
4. A microelectronic device according to claim 1, wherein the channel region includes a DWELL region having the second conductivity type.
5. A microelectronic device according to claim 1, wherein the second portion has a second dopant concentration higher than 1 × 10¹⁸ cm⁻³ and the first portion has a first dopant dose lower than 1 × 10¹³ cm⁻² .
6. A microelectronic device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.
7. A microelectronic device according to claim 1, further comprising a silicide shielding layer on the first portion of the gate electrode.
8. A microelectronic device according to claim 1, wherein the gate electrode field plate extends from the first portion of the gate electrode toward the drain region, the gate electrode field plate rests on a field relaxation dielectric layer, and the gate electrode field plate has the second conductivity type and the same dopant concentration as the first portion.
9. A microelectronic device according to claim 1, wherein the third portion of the gate electrode extends from the second portion toward the source region, and the third portion has the first conductivity type.
10. A microelectronic device according to claim 1, wherein the microelectronic device is selected from the group consisting of metal oxide semiconductor transistors, laterally diffused metal oxide semiconductor (LDMOS) transistors, drain-extended metal oxide semiconductor (DENMOS) transistors, gate bipolar semiconductor devices, gate unipolar semiconductor devices, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor (MOS) triggered SCRs, MOS-controlled thyristors, and gate diodes.
11. A microelectronic device according to claim 1, wherein the gate electrode comprises a semiconductor layer selected from the group consisting of polysilicon, polySiGe, polyGe, and polySiC.
12. A method for forming a microelectronic device, To form a source region and a drain region having a first conductivity type that extend into a semiconductor substrate having a second conductivity type opposite to the first, A gate electrode is formed on the semiconductor substrate between the source region and the drain region, Includes, A method wherein the gate electrode has a first portion and a second portion having the second conductivity type, the first portion being located between the second portion and the drain region and having a first dopant concentration, and the second portion having a second, even higher dopant concentration.
13. A method according to claim 12, further comprising forming a drain drift region having the first conductivity type within the semiconductor substrate, extending from the drain region toward the source region, extending below the first portion, and terminating before the second portion, wherein the drain drift region has an average dopant concentration lower than the average dopant concentration of the drain region.
14. A method according to claim 12, further comprising forming a field relaxation dielectric layer on a drain drift region, wherein the field relaxation dielectric layer extends from the gate dielectric layer toward the drain region and has a thickness greater than the thickness of the gate dielectric layer.
15. A method according to claim 12, further comprising forming a DWELL in the semiconductor substrate having the second conductivity type and extending from the source region below the second portion toward the drain region.
16. A method according to claim 12, further comprising forming a second portion having a second dopant concentration greater than 1 × 10¹⁸ cm⁻³ and a first portion having a first dopant dose less than 1 × 10¹³ cm⁻² .
17. A method according to claim 12, further comprising forming a silicide shielding layer on the first portion of the gate electrode, leaving a certain area of the second portion uncovered by the silicide shielding layer.
18. A method according to claim 12, further comprising forming a gate electrode field plate extending from the first portion of the gate electrode toward the drain region, wherein the gate electrode field plate rests on a field relaxation dielectric layer, and the gate electrode field plate has the second conductivity type and the same dopant concentration as the first portion.
19. A method according to claim 12, further comprising forming a third portion of the gate electrode extending from the second portion toward the source region, wherein the third portion has the first conductivity type and a doping concentration higher than 1 × 10¹⁸ cm⁻³ .
20. A method according to claim 12, wherein the first portion of the gate electrode is doped by in situ doping of the polysilicon layer on which the first portion is formed.

Description

This disclosure relates to the field of microelectronic devices. More specifically, this disclosure relates to, but is not limited to, gate devices such as MOS transistors. Semiconductor components are continuously being improved to operate reliably with smaller feature sizes. Manufacturing increasingly high-performance semiconductor devices while meeting reliability specifications is challenging. This abstract is provided to introduce a concise excerpt of the disclosed concepts, including the provided drawings, which further describe the embodiments for carrying out the invention. This abstract is not intended to limit the scope of the claimed subject matter. The disclosed examples include microelectronic devices, such as integrated circuits. One such example includes a source region and a drain region extending into a semiconductor substrate, the semiconductor substrate having a second conductivity type, and the source and drain regions having the opposite first conductivity type. A channel region having the second conductivity type extends between the source and drain regions. A gate electrode on the channel region has a first portion and a second portion. The first portion has the second conductivity type and a first dopant concentration. The second portion extends from the first portion toward the source region and has the second conductivity type and a second, even higher dopant concentration. The disclosed examples further include methods for forming integrated circuits. In one example, a method includes forming a source region and a drain region having a first conductivity type, extending into a semiconductor substrate having an opposite second conductivity type. A gate electrode is formed on the semiconductor substrate between the source region and the drain region, and the gate electrode has a first portion and a second portion having a second conductivity type. The first portion lies between the second portion and the drain region and has a first dopant concentration, and the second portion has a second, even higher dopant concentration. This is a cross-sectional view of an exemplary microelectronic device, including a transistor with a depletable resurf gate electrode at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor with a depletable resurf gate electrode at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor with a depletable resurf gate electrode at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor with a depletable resurf gate electrode at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor with a depletable resurf gate electrode at various stages of formation.This is a cross-sectional view of an exemplary microelectronic device, including a transistor with a depletable resurf gate electrode at various stages of formation. Figures 1A to 1F are graphs showing gate electrode doping profiles for exemplary microelectronic devices equipped with depletable resurf gate electrodes. This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation.This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation.This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation.This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation.This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation.This is a cross-sectional view of an LDMOS transistor equipped with a depletable resurf gate electrode at various stages of formation. Figures 3A to 3F are graphs showing gate electrode doping profiles for LDMOS transistors equipped with depletable resurf gate electrodes. This is a top view of an LDMOS transistor with a depletable resurface gate electrode in a racetrack configuration. This is a cross-sectional view of a DENMOS transistor equipped with a depletable resurf gate electrode. This graph compares the electric field in the channel under the gate electrode between the source and drain regions for a reference transistor and a transistor equipped with a depletable resurface gate electrode. This is a graph of a depletion-capable resurf gate electrode LDMOS transistor. This disclosure is described in relation to the accompanying drawings. The drawings are not drawn to scale and are provided solely for illustrative purposes. Several aspects of this disclosure are described below with reference to illustrative examples of application. It should be understood that many specific deta