JP-2026514513-A - Semiconductor device having a hybrid junction layer and its fabrication process

Abstract

At least one aspect of this disclosure relates to a semiconductor device. The semiconductor device includes a first substrate including a first region and a second region; a second substrate including a third region and a fourth region; a first junction layer including a first dielectric material for bonding the first region to the third region; and a second junction layer including a second dielectric material for bonding the second region to the fourth region. The first dielectric material is different from the second dielectric material.

Inventors

• チェ，ス ドゥ
• バロン，マシュー
• ギルデイ，アダム

Assignees

• 東京エレクトロン株式会社
• トーキョー エレクトロン ユーエス ホールディングス，インコーポレーテッド

Dates

Publication Date

20260511

Application Date

20240216

Priority Date

20230428

Claims (20)

1. It is a semiconductor device, A first substrate including a first region and a second region, A second substrate including a third region and a fourth region, A first bonding layer comprising a first dielectric material that bonds the first region to the third region, A second bonding layer comprising a second dielectric material that bonds the second region to the fourth region, Equipped with, A semiconductor device in which the first dielectric material is different from the second dielectric material.
2. The first substrate described above is A first dielectric layer disposed on the first substrate, A first interconnection structure extending through the first bonding layer into the first dielectric layer and having a first upper surface that does not overlap the first bonding layer, A second interconnection structure extending into the first dielectric layer through the second junction layer and having a second upper surface where the second junction layer does not overlap, A semiconductor device according to claim 1, including the above.
3. The second substrate is A second dielectric layer disposed on the second substrate, A third interconnection structure extending through the first junction layer into the second dielectric layer and having a third upper surface that does not overlap the first junction layer, A fourth interconnection structure extending through the second junction layer into the second dielectric layer and having a fourth upper surface that does not overlap the second junction layer, A semiconductor device according to claim 2, including the above.
4. The semiconductor device according to claim 3, wherein the first upper surface and the third upper surface are in contact with each other, the first interconnection structure is in contact with the third interconnection structure, and the second upper surface and the fourth upper surface are in contact with each other, the second interconnection structure is in contact with the fourth interconnection structure.
5. The semiconductor device according to claim 4, wherein the first bonding layer surrounds a portion of the combined sidewall of the contacting first and third interconnection structures.
6. The semiconductor device according to claim 4, wherein the second bonding layer surrounds a portion of the combined sidewall of the contacting second and fourth interconnection structures.
7. The semiconductor device according to claim 4, wherein each of the first substrates includes a plurality of first logic devices within the first region and a plurality of first memory cells within the second region.
8. The semiconductor device according to claim 7, wherein each of the second substrates includes a plurality of second logic devices within the third region and a plurality of second memory cells within the fourth region.
9. The semiconductor device according to claim 8, wherein the first interconnection structure is electrically coupled to at least one of the plurality of first logic devices, and the third interconnection structure is electrically coupled to at least one of the plurality of second logic devices.
10. The semiconductor device according to claim 8, wherein the second interconnection structure is not electrically coupled to any of the plurality of first memory cells, and the fourth interconnection structure is not electrically coupled to any of the plurality of second memory cells.
11. The semiconductor device according to claim 1, wherein the first dielectric material contains silicon carbonitride and the second dielectric material contains a high-k dielectric.
12. The semiconductor device according to claim 1, wherein the first dielectric material contains silicon carbonitride and the second dielectric material contains silicon oxide.
13. It is a semiconductor device, Each includes a first substrate containing a first interconnection structure and a second interconnection structure within a first region and a second region, A second substrate comprising a third region and a fourth region, respectively, containing a third interconnection structure and a fourth interconnection structure, wherein the first interconnection structure is in contact with the third interconnection structure and the second interconnection structure is in contact with the fourth interconnection structure, A first bonding layer comprising a first dielectric material that bonds the first region to the third region, A second bonding layer comprising a second dielectric material that bonds the second region to the fourth region, Equipped with, A semiconductor device in which the first dielectric material is different from the second dielectric material.
14. The semiconductor device according to claim 13, wherein the first dielectric material contains silicon carbonitride and the second dielectric material contains a high-k dielectric.
15. The semiconductor device according to claim 13, wherein the first dielectric material contains silicon carbonitride and the second dielectric material contains silicon oxide.
16. The semiconductor device according to claim 13, wherein each of the first substrates includes a plurality of first logic devices in the first region and a plurality of first memory cells in the second region, and each of the second substrates includes a plurality of second logic devices in the third region and a plurality of second memory cells in the fourth region.
17. The semiconductor device according to claim 16, wherein the first interconnection structure is electrically coupled to at least one of the plurality of first logic devices, the third interconnection structure is electrically coupled to at least one of the plurality of second logic devices, the second interconnection structure is not electrically coupled to any of the plurality of first memory cells, and the fourth interconnection structure is not electrically coupled to any of the plurality of second memory cells.
18. A method for manufacturing semiconductor devices, A first substrate including a first dielectric layer is prepared, A first junction layer containing the first dielectric material and a second junction layer containing the second dielectric material are superimposed on the first region and the second region of the first dielectric layer, respectively. A second substrate including a second dielectric layer is prepared, A third junction layer containing the first dielectric material and a fourth junction layer containing the second dielectric material are superimposed on the third and fourth regions of the second dielectric layer, respectively. The first substrate is bonded to the second substrate through the first to fourth bonding layers, such that the first region is bonded to the third region and the second region is bonded to the fourth region. Includes, A method wherein the first dielectric material is different from the second dielectric material.
19. The method according to claim 18, wherein the first dielectric material contains silicon carbonitride, and the second dielectric material contains a high-k dielectric or silicon oxide.
20. A first interconnection structure is formed within the first region, extending through the first junction layer into the first dielectric layer, A second interconnection structure is formed within the second region, extending through the second junction layer into the first dielectric layer, A third interconnection structure is formed within the third region, extending through the third junction layer into the second dielectric layer, A fourth interconnection structure is formed within the fourth region, extending through the fourth junction layer into the second dielectric layer, It further includes, The method according to claim 18, wherein, after the step of joining the first substrate to the second substrate, the first interconnection structure is in contact with the third interconnection structure and the second interconnection structure is in contact with the fourth interconnection structure, respectively.

Description

(Cross-reference of related patents and applications) This application claims the benefits of U.S. Nonprovisional Patent Application No. 18/309,678, filed on 28 April 2023, which is incorporated herein by reference in its entirety. (Technical fields of this disclosure) This disclosure relates to a semiconductor device and a method for joining multiple semiconductor substrates. Typically, in semiconductor devices, various electronic components (e.g., transistors, diodes, resistors, capacitors, and similar components) are formed on a semiconductor wafer. These semiconductor wafers (or one or more of their respective device dies) can then be joined to each other to form a functional device. These semiconductor wafers (or device dies) can be joined together using any of the various joining techniques for forming a functional device (e.g., stacked on top of each other). Figure 1 shows a flowchart illustrating a method for forming a semiconductor device having a hybrid junction layer according to various embodiments.Figure 2 shows an exemplary top view of a semiconductor substrate that can be implemented in the method of Figure 1 according to various embodiments.Figure 3 shows cross-sectional views of the device during various manufacturing stages of the method shown in Figure 1, according to various embodiments.Figure 4 shows cross-sectional views of the device during various manufacturing stages of the method of Figure 1, according to various embodiments.Figure 5 shows cross-sectional views of the device during various manufacturing stages of the method of Figure 1, according to various embodiments.Figure 6 shows cross-sectional views of the device during various manufacturing stages of the method of Figure 1, according to various embodiments.Figure 7 shows cross-sectional views of the device during various manufacturing stages of the method of Figure 1, according to various embodiments.Figure 8 shows cross-sectional views of the device at various stages of the manufacturing process of the method shown in Figure 1, according to various embodiments.Figure 9 shows cross-sectional views of the device during various manufacturing stages of the method of Figure 1, according to various embodiments.Figure 10 shows cross-sectional views of a device during various manufacturing stages of the method of Figure 1, according to various embodiments.Figure 11 shows a flowchart illustrating a method for forming a semiconductor device having a hybrid junction layer according to various embodiments.Figure 12 shows cross-sectional views of the device during various manufacturing stages of the method shown in Figure 11, according to various embodiments.Figure 13 shows cross-sectional views of the device during various manufacturing stages of the method shown in Figure 11, according to various embodiments.Figure 14 shows cross-sectional views of the device during various manufacturing stages of the method shown in Figure 11, according to various embodiments.Figure 15 shows cross-sectional views of the device during various manufacturing stages of the method shown in Figure 11, according to various embodiments.Figure 16 shows cross-sectional views of the device during various manufacturing stages of the method shown in Figure 11, according to various embodiments.Figure 17 shows cross-sectional views of the device during various manufacturing stages of the method shown in Figure 11, according to various embodiments.Figure 18 shows cross-sectional views of the device during various manufacturing stages of the method shown in Figure 11, according to various embodiments.Figure 19 shows cross-sectional views of the device during various manufacturing stages of the method shown in Figure 11, according to various embodiments. In the following, exemplary embodiments depicted in the drawings will be described using specific terminology. However, it will be understood that this is not intended to limit the claims or the scope of this disclosure. Modifications and further alterations to the features of the invention illustrated herein, as well as further uses of the principles of the subject matter illustrated herein, which can be conceived by those skilled in the art, are included within the scope of the subject matter disclosed herein. Other embodiments may be used and/or other modifications may be made without departing from the spirit or scope of this disclosure. The exemplary embodiments described in the detailed description are not intended to limit the subject matter presented. To continue scaling the power-performance-area-cost (PPAC) of complex circuits, such as in System-on-Chip (SoC) implementations, wafer-to-wafer bonding and chip-to-chip bonding are being employed. Many bonding techniques utilize inter-dielectric bonding to form integrated interconnect structures through hybrid bonding techniques that enable the formation of interconnects at the bonding interface between two wafers or dies. Current technologies typically use a sin