JP-7854749-B2 - Hardware-aided software modem

Inventors

• 檜山 竹生
• 大山 茂郎
• 池田 博樹

Assignees

• 株式会社マグナ・ワイヤレス

Dates

Publication Date

20260507

Application Date

20250618

Claims (1)

1. A hardware-aided software modem comprising a processor, a plurality of macro processing circuits that perform some of the processing of modem signal processing, and a memory storing a modem software program that causes the processor to perform at least the remaining processing of the modem signal processing, excluding the aforementioned partial processing; wherein the processor is equipped with a plurality of control arithmetic cores that cooperate with the macro processing circuits, and each of the plurality of macro processing circuits and control arithmetic cores is pipelined to ensure uniform processing time for modem signal processing.

Description

This invention relates to a hardware-aided software modem that implements a modem used in mobile phones and the like using software. Historically, modems have evolved from the early 300bps data modems of the late 1960s to the 4800bps digital modems for facsimile machines in the 1970s, and to hundreds of Mbps in today's mobile phone era. 5G communication is aiming for even higher speeds of gigabps. Regarding the technology that constitutes a modem, since the digital modem era, while dedicated LSIs have become common as speeds have increased, there are also software-defined modems. Software-defined modems have lower processing speeds, i.e., lower communication speeds compared to dedicated LSIs, but they have advantages such as lower cost and the ability to incorporate application software that utilizes the modem. As shown in Reference 1, some software modems are designed to consist only of a CPU and memory as hardware, with clever software processing methods such as interrupt handling. However, to achieve higher speeds, CPUs with numerous cores are used, or special CPUs with a structure that allows for parallel processing using many cores, such as GPUs (Graphics Processing Units), are employed. On the other hand, regardless of modems, pipeline processing, which allows multiple instructions to be executed in parallel, has long been used to speed up computer processing. This invention, however, makes pipeline processing more efficient. Japanese Patent Publication No. 2001-197128 Figure 1 shows a typical configuration of a software modem.Figure 2 shows the signal processing flow of the modem according to the present invention.Figure 3 shows the hardware configuration of the software modem according to the present invention.Figure 4 shows how the software processing of the macro circuit according to the present invention is pipelined.Figure 5 shows an example where the processing times for pipeline processing are inconsistent. Figure 1 shows a simplified general configuration of a software modem. Like a personal computer, it has a CPU and memory (labeled MEMORY in the figure). The modem software, along with the operating system (OS) that runs the computer, is installed within the MEMORY as application software. The DAC/ADC in Figure 1 refers to a component that converts digital data processed by the computer into analog data for transmission, generating the modem's output signal. Conversely, it also has an analog-to-digital conversion function, converting the received analog input signal into digital data for processing by the computer. Today, CPU performance has improved by incorporating multiple cores, such as six, but the communication speed of modems remains limited to a few Mbps, a speed typical of 3G mobile phones. On the other hand, as seen in recent 4G (LTE) communications, video streaming now requires communication speeds of several hundred Mbps from modems. Figure 2 shows the signal processing flow (modem signal processing) in a mobile phone modem, with the left side being the transmitting side and the right side being the receiving side. On the transmitting side, user data is divided into predetermined lengths and framed. For each frame, a redundant error detection code called CRC is added by the CRC addition unit 1 to detect errors that may occur during communication, thus formatting the frame signal. The encoding unit 2 performs a Forward Error Correction (FEC) function as a countermeasure against transmission errors, and the data is encoded using LDPC (Low-Density Parity Check) code or turbo code. In the scrambling section 3, data is randomized to ensure uniform radio energy distribution, and the encoding efficiency using LDPC coding is improved (e.g., by avoiding the creation of unusual patterns such as consecutive zeros). Subsequently, in the modulation section 4, multiple bits from the scrambling section output are combined into a single symbol, and a coordinate point in two-dimensional coordinates for QAM (quadrature amplitude modulation) is determined for each symbol. In this invention, there are 64 coordinate points, and each symbol consists of 6 bits of data, resulting in 64QAM. In the precoding section 5, for MIMO (Multiple Input and Multiple Output) control, spatial channels are formed orthogonally to each other for the multiple antennas used, and weighting is performed to appropriately control the transmission power allocated to each channel. In the resource element mapping unit 6, the output data from the pre-coding unit is converted to a multi-carrier format and frequency-division multiplexed. The IFFT (Inverse Fast Fourier Transform) unit 7 converts the data sequence from frequency space to time space, and the DAC unit 8 converts the digital data to analog, which is then transmitted as radio waves. On the receiving end, the ADC unit 17 first converts the analog radio waves to digital, the FFT (Fast Fourier Transform) unit 16 converts the data sequence from time-space to frequency-space,