JP-7854824-B2 - Sensor device and semiconductor device requiring said sensor device

JP7854824B2JP 7854824 B2JP7854824 B2JP 7854824B2JP-7854824-B2

Inventors

挽地友生

Assignees

エイブリック株式会社

Dates

Publication Date: 20260507
Application Date: 20220322

Claims (7)

A sensor device that determines the detection of a physical quantity by detecting that physical quantity multiple times in succession, A first determination circuit determines whether the detection of the physical quantity has occurred twice in a row, including the current and the previous instance, based on the signal level of the detection result signal output from a sensor element that outputs a detection result signal representing the detection result of the physical quantity, and outputs an initialization signal including the signal level corresponding to the determination result. A second determination circuit has a counter that initializes the count if the initialization signal indicates that the physical quantity has not been detected twice in a row, and continues counting up to a set number of times if the physical quantity has been detected twice in a row, and outputs an output latch signal that includes a signal level corresponding to whether the count of the counter has continuously matched up to the set number of times, An output register that switches the signal level of the output signal supplied to the output terminal in accordance with the change in the signal level of the output latch signal, A sensor device characterized by comprising the following features.
The first determination circuit is, An input terminal to which a binarized signal is supplied according to the signal level of the detection result signal, The output terminal that outputs the initialization signal, A first flip-flop circuit includes a first input terminal connected to the input terminal of the first determination circuit, a second input terminal to which a clock signal is supplied, and an output terminal that outputs a signal including a signal level corresponding to the signal levels of the signals supplied to its own first and second input terminals. A second flip-flop circuit includes a first input terminal connected to the output terminal of the first flip-flop circuit, a second input terminal to which a clock signal is supplied, and an output terminal that outputs a signal including a signal level corresponding to the signal levels of the signals supplied to its own first and second input terminals. A logic circuit including a first input terminal connected to the output terminal of the first flip-flop circuit and the first input terminal of the second flip-flop circuit, a second input terminal connected to the output terminal of the second flip-flop circuit, and an output terminal connected to the output terminal of the first decision circuit, A sensor device according to claim 1, having the following features.
The second determination circuit described above is: The output terminal connected to the aforementioned output register, The counter includes an output terminal that outputs a signal representing the count obtained by counting the number of times the above two matches occurred consecutively, A continuous match determination circuit includes an input terminal connected to the output terminal of the counter, and an output terminal that outputs a match determination flag signal including a signal level corresponding to the determination result of whether or not a continuous match has occurred up to the number of times set based on the count, A first AND circuit includes a first input terminal to which a clock signal is supplied, a second input terminal connected to the output terminal of the continuous match determination circuit, and an output terminal connected to the output terminal of the second determination circuit, and supplies a signal including a signal level corresponding to the result of an AND operation between the supplied match determination flag signal and the clock signal as an output latch signal from the output terminal to the output terminal of the second determination circuit, A sensor device according to claim 1 or claim 2, having the following features.
The sensor device according to claim 3, wherein the continuous match determination circuit has a correspondence between the signal level of the match determination flag signal and the count number obtained from the signal representing the count number, and has a decoder that outputs the output latch signal including the signal level corresponding to the count number according to the correspondence.
If the number of times mentioned above is a power of 2 or more, The sensor device according to claim 3, wherein the continuous match determination circuit is connected to the output terminal of the counter and has a second AND circuit that includes the same number of input terminals as the number of bits of the counter and an output terminal that performs an AND operation on the signals supplied to each input terminal and outputs the result.
The counter has at least k flip-flop circuits, If k is a natural number and N is a natural number representing the number of times, The aforementioned k is calculated using the ceiling function ceiling(log2N), which represents the smallest integer greater than or equal to log2N for a real number log2N. k=ceiling(log2N) A sensor device according to any one of claims 1 to 5, represented by [the specified formula].
A semiconductor device comprising a semiconductor substrate on which a sensor device according to any one of claims 1 to 6 is formed.

Description

This invention relates to a sensor device and a semiconductor device equipped with the sensor device. In sensor devices, such as magnetic sensors, and semiconductor devices equipped with such sensors, fluctuations in detection and judgment results due to noise are suppressed by sequentially latching multiple logic outputs from the sensor, etc., in a register and performing a match determination (see, for example, Patent Document 1). To improve the reliability of the detection and judgment results, increasing the number of match determinations is effective. In the circuit described in Patent Document 1, the number of match determinations is set to three using a two-bit register. Japanese Patent Application Publication No. 3-252526 This is a schematic block diagram showing an example of the circuit configuration of a sensor device and a semiconductor device equipped with the sensor device according to an embodiment of the present invention.This is a schematic block diagram showing an example of the circuit configuration of the sensor device and the first determination circuit of the semiconductor device equipped with the sensor device according to this embodiment.This is a schematic block diagram showing an example of the circuit configuration of a counter in the second determination circuit of a sensor device and a semiconductor device equipped with the sensor device according to this embodiment.(A) is a diagram showing the relationship between the detection result signal and the magnetic flux density of the sensor device and the semiconductor device equipped with the sensor device according to this embodiment, and (B) is a diagram showing the relationship between the output signal and the magnetic flux density of the semiconductor device according to this embodiment.This is a timing diagram of the semiconductor device according to this embodiment. Hereinafter, a sensor device and a semiconductor device equipped with the sensor device according to an embodiment of the present invention will be described with reference to the drawings. Figure 1 is a block diagram showing an example of the circuit configuration of a sensor device 10 and a semiconductor device 1, which are embodiments of the present invention. Here, the X, Y, and Z axes shown in Figure 1 are the coordinate axes of a mutually orthogonal three-dimensional Cartesian coordinate system. The X-Y plane is parallel to the surface of the semiconductor substrate 2 (the surface facing the viewer in Figure 1). That is, the surface of the semiconductor substrate 2 has the Z axis as its normal vector. The semiconductor device 1 comprises a semiconductor substrate 2 on which a sensor device 10 is formed in a semiconductor region. The semiconductor substrate 2 is provided with a power terminal 3 connected to a first power supply and a power terminal 4 connected to a second power supply. The sensor device 10 is a device that determines the detection of a physical quantity by determining that the physical quantity has been detected multiple times consecutively. Here, the number of times set as the upper limit for counting the detection of the physical quantity is defined as "N times". N is a natural number greater than or equal to 2. The sensor device 10 comprises a Hall element 20, a binarization circuit 30, a determination circuit 40, a determination circuit 50, and an output register 90. The Hall element 20, used as a sensor element, is an example of a magnetic sensor element. The Hall element 20 shown in the figure is a so-called horizontal Hall element that outputs a signal S01 corresponding to the magnetic flux density B acting perpendicular to the semiconductor substrate 2, i.e., in the Z direction. The binarization circuit 30 is a circuit that converts a detection result signal S01, which includes a low level (hereinafter referred to as "L level") and a high level (hereinafter referred to as "H level"), into a binarized signal S02. Signal S02 includes two signal levels corresponding to the signal levels of signal S01; specifically, signal levels corresponding to whether or not the current pole detection state matches the magnetic flux density B. The binarization circuit 30 has an input terminal connected to the output terminal of the Hall element 20 and an output terminal that outputs signal S02. The first determination circuit, determination circuit 40, determines whether the detection of magnetic flux density B as a physical quantity has occurred twice consecutively (this time and the time immediately preceding it) based on the input signal S02, and outputs a signal S05 containing the signal level corresponding to the determination result. The determination circuit 40 has an input terminal 40a to which signal S02 is supplied, an input terminal 40b to which the clock signal CLK is supplied, an input terminal 40c to which the reset signal RST is supplied, and an output terminal 40d to which the initialization signal S05 is output. The input terminal 40a