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JP-7855051-B1 - Error measuring device and error measuring method

JP7855051B1JP 7855051 B1JP7855051 B1JP 7855051B1JP-7855051-B1

Abstract

[Problem] To provide an error measurement device and error measurement method that can display a reliability level in accordance with the measurement conditions when executing the matrix scan function. [Solution] The error measurement device displays a matrix scan display screen 40 that displays information related to the matrix scan function. The matrix scan display screen 40 includes a spin box 44 for inputting the measurement time of the signal under test, spin boxes 52a and 52b for inputting the allowable error rate of the signal under test, a spin box 53 for inputting the allowable number of errors during the measurement time of the signal under test, and a text box 51 for displaying the reliability level. The error measurement device calculates the reliability level based on the data rate of the signal under test and the measurement time, the allowable error rate, and the allowable number of errors input to the matrix scan display screen 40. [Selection Diagram] Figure 2

Inventors

  • 伊藤 充貴
  • 岩井 達也
  • 吉岡 宏紀

Assignees

  • アンリツ株式会社

Dates

Publication Date
20260507
Application Date
20241114

Claims (4)

  1. An error measuring device ( 1 ) performs a matrix scan function that measures the number of errors and the error rate of the measured signal by sending a test signal to the object under test (100) during link training, based on the parameter values of the cells to be scanned, which are selected and set from a triangular matrix of combinations of coefficient values C -2, C -1, and C +1 in the Full Swing value defined in the PCI Express standard, and receiving the measured signal that is folded back from the object under test in conjunction with the transmission of the test signal, A display control unit (17) displays the coefficient values of C -2 in a selectable manner using a number of tabs corresponding to the Full Swing value, and displays each combination of the coefficient values of C -2 in the selected tab, each coefficient value of C +1 , and each coefficient value of C - 1 as a cell in a matrix on the display screen, and displays C-2, C-1, and C + 1 in a three-dimensional overview on the display screen with C + 1 as the horizontal coordinate axis, C -1 as the vertical coordinate axis, and C -2 as the depth coordinate axis. An operation display unit (32) for selecting and setting a range that includes at least one of the cells to be scanned in the matrix display or the overview display, A control unit (15) that executes the matrix scan function using parameter values within the range selected and set on the operation display unit, An error measurement unit (14) measures the number of errors and the error rate of the signal under measurement over a predetermined measurement period, The system includes a reliability level calculation unit (20) that calculates a target reliability level related to the allowable value of the error rate of the signal under measurement, The aforementioned display screen is A measurement time input unit (44) for inputting the measurement time of the signal to be measured, A target error rate input unit (52a, 52b) for inputting the allowable value of the error rate of the signal under measurement, A target error input unit (53) for inputting an acceptable value for the number of errors during the measurement time of the signal under measurement, It includes a reliability level display unit (51) that displays the target reliability level, The error measurement device is characterized in that the reliability level calculation unit calculates the target reliability level based on the data rate of the signal to be measured, the measurement time, the allowable value of the error rate, and the allowable value of the number of errors, which are input to the display screen.
  2. The error measuring device according to claim 1, characterized in that the reliability level calculation unit calculates the target reliability level by substituting the product of the data rate and the measurement time into N in the following formula (2), substituting the allowable value of the error rate into ER S in the following formula (2), and substituting the allowable value of the number of errors into E in the following formula (2).
  3. The error measuring device according to claim 1 or 2, further comprising a result output unit (21) that outputs the allowable value of the error rate, the allowable value of the number of errors, and the target reliability level displayed on the display screen in a predetermined file format.
  4. An error measurement method that performs a matrix scan function to measure the number of errors and error rate of the measured signal , which is configured by sending a test signal to the object under test ( 100 ) during link training based on parameter values of the cells to be scanned, selected from a triangular matrix of combinations of coefficient values C-2, C-1, and C+1 in the Full Swing value defined in the PCI Express standard, receiving the measured signal folded back from the object under test in conjunction with the transmission of the test signal, and measuring the number of errors and error rate of the measured signal, Step (S1) displays the coefficient value of C -2 in a selectable manner using a number of tabs corresponding to the Full Swing value, Step (S1) is to display each combination of the coefficient value of C -2 of the selected tab, each coefficient value of C +1 , and each coefficient value of C -1 as a cell in a matrix on the display screen, Step (S1) is to display C -2 , C -1 , and C +1 in a three-dimensional overhead view on the display screen, with C + 1 being the horizontal coordinate axis, C- 1 being the vertical coordinate axis, and C - 2 being the depth coordinate axis. Step (S2) of selecting and setting a range that includes at least one of the cells to be scanned in the matrix display or the overview display, A reliability level calculation step (S3) for calculating a target reliability level related to the allowable error rate of the signal under measurement, Step (S4) of displaying the target reliability level on the display screen, The steps include (S5 to S7) executing the matrix scan function using the parameter values within the selected range, The step of performing the matrix scan function includes an error measurement step (S7) of measuring the number of errors and the error rate of the signal under measurement over a predetermined measurement time, The aforementioned display screen is A measurement time input unit (44) for inputting the measurement time of the signal to be measured, A target error rate input unit (52a, 52b) for inputting the allowable value of the error rate of the signal under measurement, A target error input unit (53) for inputting an acceptable value for the number of errors during the measurement time of the signal under measurement, It includes a reliability level display unit (51) that displays the target reliability level, The error measurement method is characterized in that the reliability level calculation step calculates the target reliability level based on the data rate of the signal under measurement, the measurement time, the allowable value of the error rate, and the allowable value of the number of errors, which are input to the display screen.

Description

This invention relates to an error measurement device and method for measuring the number of errors and error rate of a signal under test (Device Under Test: DUT) during link training in a state where the DUT is in a signal pattern folding state. The device transmits a test signal to the DUT based on parameter values defined, for example, by the PCI Express 6.0 standard (hereinafter also referred to as the PCIe Gen6 standard), receives the signal folded back from the DUT in response to the transmission of the test signal, and measures the number of errors and the error rate of the signal under test. Error measurement devices are conventionally known as devices that transmit a test signal of a known pattern containing fixed data to a DUT (Dynamic Output Tracker), and then compare the signal under test, received back from the DUT, with a reference signal on a bit-by-bit basis to measure the number of errors and the error rate of the signal under test. For example, when testing whether a DUT (Device Under Test) complies with communication standards such as PCI Express, the error measurement device performs emphasis adjustment of the DUT's output waveform during link training. To ensure communication quality between the error measurement device and the DUT (the link partner), it is necessary to select the optimal combination of emphasis in the error measurement device's transmitter and equalizer in the DUT's receiver. Therefore, a matrix scan function is used that scans the emphasis settings of the transmitter section of the error measurement device to find the optimal setting for the DUT's receiver section, automatically searching for the best setting for the DUT's receiver section (see, for example, Patent Document 1). The matrix scan function allows for the simultaneous measurement of many errors. Here, the confidence level (CL) for the error rate of the signal under test is defined by the following equation (1). The confidence level represents the probability that the true error rate of the signal under test is less than the predefined target BER (Bit Error Rate). In addition, in equation (1), N: Bitrate [bit/s] × Measurement time [s] (Number of bits measured) BER S : Target BER E: This is the target number of errors. Japanese Patent Publication No. 2024-022235 This is a block diagram showing the configuration of an error measuring device according to an embodiment of the present invention.This figure shows the matrix scan display screen when the [Measurement] tab is selected in the error measurement device according to the present invention.This figure shows the matrix scan display screen when the [Starting Preset] tab is selected in the error measurement device according to the present invention.This figure shows the matrix scan display screen when the [Scan] tab is selected in the error measurement device according to the present invention.This figure shows an example of a matrix scan editing screen in the error measurement device according to the present invention.This figure shows an example of the contents of a file output from the result output unit of the error measurement device according to the present invention.This flowchart shows the process of an error measurement method using an error measurement device according to an embodiment of the present invention.This figure shows a preset table of coefficient values defined in the PCIe Gen6 standard. The following describes embodiments of the error measurement device and error measurement method according to the present invention, with reference to the drawings. [Summary of the present invention] The error measurement device according to the present invention uses a device compliant with the PCIe Gen6 standard as shown in PCI Express Base Specification Revision 6.0 16 December 2021 as the device under test (DUT), for example, as a connection standard for expansion buses and expansion slots. During link training in which the DUT is in a signal pattern folding state, a test signal based on parameter values defined in the PCIe Gen6 standard is transmitted to the DUT, and the number of errors and error rate of the signal under test, which is folded back from the DUT in conjunction with the transmission of this test signal, are measured. Furthermore, section 8.3.3.3 Tx Equalization Presets for 8.0, 16.0, 32.0, 1, and 64.0 GT/s of the PCIe Gen 6 standard includes descriptions of emphasis preset values, as shown in Figure 8-6 Definition of Tx Voltage Levels and Equalization Ratios, Table 8-1 Tx Preset Ratios and Corresponding Coefficient Values for 8.0, 16.0, and 32.0 GT/s, and Table 8-2 Tx Preset Ratios and Corresponding Coefficient Values for 64.0 GT/s (see Figure 8). Furthermore, section 8.3.3.8 Coefficient Range and Tolerance for 8.0, 16.0, 32.0, 1, and 64.0 GT/s of the PCIe Gen 6 standard includes a description of a triangular matrix table, as shown in Figure 8-10, Transmit Equalization Coefficient Space Triangular Matrix Example for 64.0 GT/s. The mat