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JP-7855065-B2 - Bias voltage generation circuit and electronic circuit

JP7855065B2JP 7855065 B2JP7855065 B2JP 7855065B2JP-7855065-B2

Inventors

  • 丹治 景斉

Assignees

  • 日清紡マイクロデバイス株式会社

Dates

Publication Date
20260507
Application Date
20220518

Claims (17)

  1. A first constant current source that supplies a first constant current, A second constant current source that supplies a second constant current smaller than the first constant current, A bias voltage generation circuit comprising at least one first MOS transistor and a bias voltage generation unit that generates a predetermined bias voltage based on the second constant current or the first and second constant currents, wherein the bias voltage generation circuit is for an electronic circuit to which current is supplied by a current mirror circuit composed of the first MOS transistor and at least one second MOS transistor, The bias voltage generation circuit, based on the operating mode switching control signal, (1) When the electronic circuit is not in operation, the bias voltage generation unit generates a predetermined bias voltage based on the second constant current, (2) When the electronic circuit is in operation, the bias voltage generating unit generates a predetermined bias voltage based on the first and second constant currents, or the first constant current. The bias voltage generation circuit is configured.
  2. The at least one first MOS transistor includes two MOS transistors connected in series with each other, and the control terminals of the two MOS transistors are connected to each other. The bias voltage generation circuit according to claim 1.
  3. The at least one first MOS transistor includes two MOS transistors connected in series with each other, and the two MOS transistors are each diode-connected. The bias voltage generation circuit according to claim 1.
  4. The at least one first MOS transistor includes two MOS transistors connected in parallel to each other and having different thresholds. The bias voltage generation circuit according to claim 1.
  5. The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source. The control terminal of the third MOS transistor is connected to the connection point between the second constant current source and the resistor. The bias voltage generation circuit according to claim 1.
  6. The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source. The third MOS transistor is diode-connected. The bias voltage generation circuit according to claim 1.
  7. The at least one first MOS transistor includes a third MOS transistor connected in series with a first diode connected to the second constant current source. The third MOS transistor is diode-connected. The bias voltage generation circuit according to claim 1.
  8. The at least one first MOS transistor is configured by connecting a third MOS transistor connected to the second constant current source and a second diode in series. The third MOS transistor is diode-connected. The bias voltage generation circuit according to claim 1.
  9. A first constant current source that supplies a first constant current, A second constant current source that supplies a second constant current smaller than the first constant current, An electronic circuit having a bias voltage generating circuit comprising at least one first MOS transistor and a bias voltage generating unit that generates a predetermined bias voltage based on the second constant current or the first and second constant currents, The bias voltage generation circuit is supplied with current by a current mirror circuit composed of the first MOS transistor and at least one second MOS transistor. The bias voltage generation circuit, based on the operating mode switching control signal, (1) When the electronic circuit is not in operation, the bias voltage generation unit generates a predetermined bias voltage based on the second constant current, (2) When the electronic circuit is in operation, the bias voltage generating unit generates a predetermined bias voltage based on the first and second constant currents, or the first constant current. The electronic circuit that makes up the circuit.
  10. The at least one first MOS transistor includes two MOS transistors connected in series with each other, and the control terminals of the two MOS transistors are connected to each other. The electronic circuit according to claim 9.
  11. The at least one first MOS transistor includes two MOS transistors connected in series with each other, and the two MOS transistors are each diode-connected. The electronic circuit according to claim 9.
  12. The at least one first MOS transistor includes two MOS transistors connected in parallel to each other and having different thresholds. The electronic circuit according to claim 9.
  13. The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source. The control terminal of the third MOS transistor is connected to the connection point between the second constant current source and the resistor. The electronic circuit according to claim 9.
  14. The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source. The third MOS transistor is diode-connected. The electronic circuit according to claim 9.
  15. The at least one first MOS transistor includes a third MOS transistor connected in series with a first diode connected to the second constant current source. The third MOS transistor is diode-connected. The electronic circuit according to claim 9.
  16. The at least one first MOS transistor is configured by connecting a third MOS transistor connected to the second constant current source and a second diode in series. The third MOS transistor is diode-connected. The electronic circuit according to claim 9.
  17. The aforementioned electronic circuit is a comparator circuit, a source follower circuit, a voltage generation circuit, a time constant circuit, or a differential amplifier circuit. The electronic circuit according to any one of claims 9 to 16.

Description

The present invention relates to a bias voltage generation circuit and an electronic circuit comprising the bias voltage generation circuit. It is already known that there is a demand to reduce current consumption in order to use rechargeable batteries for extended periods. For example, a method is disclosed in Patent Document 1, for instance, that selectively switches to a sleep mode in accordance with an operating mode switching control signal so that the current consumption is lower in sleep mode compared to the operating mode. The low dropout (LDO) regulator disclosed in Patent Document 1 is (1) A pass gate that controls the voltage rail to the regulator output in response to a pass gate control signal which is an operating mode switching control signal, (2) A controllable slew differential amplifier that is switchable between a slew-limited state and a full slew state, receives feedback from the regulator output, and is configured to generate the pass gate control signal at the full slew rate in the full slew state and at a reduced slew rate in the slew-limited state, based on the reference voltage and the feedback. Next, we will provide a detailed explanation using a conventional comparator circuit 100 as an example. Figure 17 is a circuit diagram showing the configuration of a conventional comparator circuit 100. Figure 18 is a timing chart of each signal showing the operation of the comparator circuit 100 in Figure 17. In Figure 17, the comparator circuit 100 is configured to include a comparator section 101 and a bias voltage generation section 102. The comparator section 101 is configured to be a typical comparator using a differential amplifier and an inverter INV1, and here the differential amplifier is configured to include MOS field-effect transistors (hereinafter referred to as MOS transistors) Q1 to Q7. In the comparator section 101, MOS transistors Q1, Q2, and Q6 are P-channel MOS transistors, and MOS transistors Q3, Q4, Q5, and Q7 are N-channel MOS transistors. The comparator circuit 100 has a non-inverting input terminal T1, an inverting input terminal T2, a block enable signal input terminal T3, and a comparison result signal output terminal T4. During the operation of the comparator section 101, a tail current Itail flows through MOS transistor Q5. The output voltage of the differential amplifier is output to the comparison result signal output terminal T4 via inverter INV1 from the connection point of the drains of MOS transistors Q6 and Q7. In the bias voltage generation unit 102, the power supply voltage VDD is connected to the sources of the MOS transistors Q1, Q2, and Q6 of the comparator unit 101, and is grounded via the constant current source CI1 that supplies the reference current IREF, and switches SW1 and SW2. The connection point of switches SW1 and SW2 generates a bias voltage VNBIAS, which is applied to the drain and gate of MOS transistor Q8 and the gates of MOS transistors Q5 and Q7. The sources of MOS transistors Q8, Q5, and Q7 are grounded. The block enable signal BLKEN, which is an operating mode switching control signal input to the block enable signal input terminal T3, is input to the control terminal of switch SW1 and also to the control terminal of switch SW2 via inverter INV2. Here, when a high-level block enable signal BLKEN is input to the block enable signal input terminal T3, switch SW1 is turned on and switch SW2 is turned off. MOS transistors Q5, Q7, and Q8 constitute a current mirror circuit, and current flows through MOS transistor Q8 according to the bias voltage VNBIAS, and a current proportional to that current flows through MOS transistors Q5 and Q7. On the other hand, when a low-level block enable signal BLKEN is input to the block enable signal input terminal T3, switch SW1 is turned off and switch SW2 is turned on. In the comparator circuit 100 configured as described above, as shown in Figure 18, when the block enable signal BLKEN is switched from L level to H level at time t1, the operating mode switches from sleep mode to startup mode. The bias voltage VNBIAS rises from a pulled-down state to the gate-source voltage Vgs of the MOS transistor Q8, which corresponds to the reference current IREF, during a startup period, and then enters active mode at time t2. In other words, the comparator circuit 100 cannot perform to its full potential without going through the startup period from time t1 to t2. The time required at this time depends on the magnitude of the reference current IREF and the parasitic capacitance value in the wiring of the bias voltage VNBIAS. Japanese Patent Publication No. 2019-053757 This is a circuit diagram showing an example of the configuration of the comparator circuit 1 according to Embodiment 1.This is a timing chart of each signal showing the operation of the comparator circuit 1 in Figure 1.This figure shows a comparison of the operation of the comparator circuit 100 according to Comparative Example 1 and the comparator