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JP-7855111-B1 - Error rate measuring device and error rate measuring method

JP7855111B1JP 7855111 B1JP7855111 B1JP 7855111B1JP-7855111-B1

Abstract

[Problem] To provide an error rate measurement device and method that can detect specific patterns such as sequence blocks in real time from input signals from an object under test equipped with a link state management mechanism, and that can clearly notify the user of the detection status of the specific pattern, including the detection timing. [Solution] The error rate measuring device 1 includes: a lead detection unit 603c that compares a reference signal with an input signal and detects the beginning of a specific pattern in the input signal; an ED 5b that processes error rate measurement of a specific pattern in the input signal by sequentially comparing a detection signal synchronized with the timing at which the lead of the specific pattern is detected by the lead detection unit 603c with the internal signal generated by the internal signal generation circuit 603a; a log information generation management unit 603g that generates log information of the detection status of the specific pattern after the lead has been detected and stores it in the data storage unit 4a; and a display unit 3 that reads out the log information and displays it based on a predetermined display request operation. [Selection Diagram] Figure 1

Inventors

  • 佐藤 遼
  • 吉岡 宏紀

Assignees

  • アンリツ株式会社

Dates

Publication Date
20260507
Application Date
20250331

Claims (7)

  1. An error rate measuring device (1) that measures the error rate of an input signal from an object (10) under test equipped with a link state management mechanism, An internal signal generation circuit (603a) generates an internal signal consisting of a specific pattern that is expected to be output from the object under test according to the state of the link state management mechanism, A reference signal holding unit (603b) holds a portion of the leading edge of the aforementioned internal signal as a reference signal, A leading detection unit (603c) compares the reference signal with the input signal to detect the leading edge of the specific pattern in the input signal, An error rate measurement unit (5b) performs error rate measurement processing of the error rate of the specific pattern in the input signal by sequentially comparing a detection signal synchronized with the timing at which the leading edge of the specific pattern is detected by the leading edge detection unit with the internal signal generated by the internal signal generation circuit, A log information generation management unit (603g) generates log information of the detection status of the specific pattern after the detection of the beginning and stores it in the data storage unit (4a), An error rate measuring device characterized by comprising a display unit (3) that reads the log information based on a predetermined display request operation and displays it on a detailed results display screen (80).
  2. The error rate measuring device according to claim 1, characterized in that the log information generation and management unit generates log information including the time when the specific pattern was detected, the count value counted from the predetermined start time of counting for the detected specific pattern, and good/bad judgment information that determines whether the error rate for the detected specific pattern was successfully obtained (Gain) or not (Loss).
  3. The system further includes a latch (603e) that holds the detection signal, The error rate measuring device according to claim 1 or 2, characterized in that the display unit displays a detection notification image (601) indicating that the leading edge of the specific pattern has been detected by the leading edge detection unit during the period in which the detection signal is held by the latch unit.
  4. The error rate measuring device according to claim 3 , characterized in that the display unit further displays a hold release instruction unit (62) for releasing the hold of the detection signal by the latch unit.
  5. The error rate measuring device according to claim 1, further comprising a delay circuit (603f) that delays the input signal in which the leading edge of the specific pattern has been detected by the leading edge detection unit, thereby synchronizing the internal signal output from the internal signal generation circuit with the specific pattern in the input signal.
  6. The error rate measuring device according to claim 1 or 2, further comprising a pulse pattern generator (5a) that transmits a sequence block for transitioning the link state management mechanism to an arbitrary state to the object under measurement.
  7. An error rate measurement method performed by an error rate measuring device (1) that measures the error rate of an input signal from an object (10) equipped with a link state management mechanism, An internal signal generation step (S3) is to generate an internal signal consisting of a specific pattern that is expected to be output from the object under measurement according to the state of the link state management mechanism, A reference signal holding step (S4) in which a portion of the beginning of the aforementioned internal signal is held as a reference signal, A leading detection step (S6) involves comparing the reference signal with the input signal to detect the beginning of the specific pattern in the input signal, An error rate measurement step (S9) is performed by sequentially comparing a detection signal synchronized with the timing at which the beginning of the specific pattern is detected in the preceding beginning detection step with the internal signal generated by the internal signal generation circuit, thereby measuring the error rate of the specific pattern in the input signal. A log information generation management step (S11) involves generating log information of the detection status of the specific pattern after the detection of the leading element and storing it in the data storage unit (4a), An error rate measurement method characterized by including a display step (S18) of reading the log information based on a predetermined display request operation and displaying it on a detailed results display screen (80).

Description

This invention relates to an error rate measuring device and an error rate measuring method having functions for generating and displaying log information indicating the reception status of the input signal pattern input from an object under measurement. Protocols such as PCIe Express (Peripheral Component Interconnect Express) (hereinafter referred to as PCIe) and USB (Universal Serial Bus) require sequential operation to control the Link Training and Status State Machine (LTSSM) and switch the device state. By sending a defined set of data patterns (hereinafter referred to as "sequence blocks") to the device in the correct order, it becomes possible to arbitrarily change the device state. For example, PCIe has standards such as Gen1 to Gen6, and the communication speeds vary considerably depending on the standard, ranging from 2.5 GT/s to 32 GT/s. All PCIe devices are backward compatible, and the communication speed can be switched. State switching is also used for this communication speed switching. For example, in PCIe, the state transition diagram for LTSSM is as shown in Figure 10, and the states defined are L0, L0s, L1, L2, Detect, Polling, Configuration, Disabled, Hot Reset, Loopback, and Recovery. Manufacturers of PCIe and USB devices, as well as their controllers, need to verify during device development testing whether the devices can correctly send and receive sequence blocks. This verification is typically performed using tools such as logic analyzers and protocol analyzers. However, these measuring devices often lack real-time capabilities and cannot simultaneously acquire and analyze data. Furthermore, some sequence blocks have very long cycles, which can make analysis time-consuming for these devices. An error rate measuring device is known as a measuring device that can acquire and analyze data simultaneously in real time (see, for example, Patent Document 1). Patent No. 7132964 This is a block diagram showing the configuration of an error rate measuring device according to an embodiment of the present invention.This figure shows an example of a result display screen shown on the display unit of an error rate measuring device according to an embodiment of the present invention.This figure shows an example of a pattern setting screen having setting functions for both the PPG side and the ED side, which is displayed on the display unit of an error rate measuring device according to an embodiment of the present invention.Figure 3 shows an example of the pattern setting screen on the ED side in the pattern setting screen shown.This figure shows an example of a sequence editing screen displayed on the display unit of an error rate measuring device according to an embodiment of the present invention.This figure shows an example of a detailed results screen that displays log information managed by the log information generation and management function of the error rate measurement device according to an embodiment of the present invention.This is a schematic diagram illustrating a method for establishing synchronization of the transmission start timing t0 of a specific pattern between the PPG and ED, where (a) shows the connection method between the PPG and ED, and (b) shows the timing of transmitted and received data.This is a flowchart illustrating the process of an error rate measurement method using an error rate measurement device according to an embodiment of the present invention.Figure 8 is a flowchart showing the processing operation of the detection notification in step S15.This diagram shows the state transitions of LTSSM. The following describes embodiments of the error rate measurement device and error rate measurement method according to the present invention, with reference to the drawings. As shown in Figure 1, the error rate measuring device 1 according to this embodiment measures the error rate of the input signal from the object under test (Device Under Test: DUT) 10, and comprises an operation unit 2, a display unit 3, a storage unit 4, a measurement unit 5, and a control unit 6. The DUT 10 is equipped with an LTSSM (Long-Term Sequence Machine), and when the LTSSM transitions to one of the states shown in Figure 10, for example, it outputs a data pattern such as a sequence block corresponding to that state as an input signal to the error rate measurement device 1. For example, when the DUT 10 transitions to the loopback state "LOOPBACK_ACTIVE_MASTER," it outputs the output signal from the pulse pattern generator (PPG) 5a (described later) as an input signal to the error rate measurement device 1. Examples of standards that the DUT 10 supports include PCIe Gen1-6, USB 3.1 (Gen1), and USB 3.2 (Gen2). In the error rate measurement device 1 shown in Figure 1, the operation unit 2 is for receiving user input and consists of a user interface such as an operation knob, various keys, switches, buttons, and a touch panel, mouse, or keyboard for operating the GUI of the display unit 3, w