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JP-7855126-B2 - Semiconductor equipment

JP7855126B2JP 7855126 B2JP7855126 B2JP 7855126B2JP-7855126-B2

Inventors

  • 白石 信仁
  • 森本 康夫
  • 船戸 是宏

Assignees

  • ルネサスエレクトロニクス株式会社

Dates

Publication Date
20260507
Application Date
20250716

Claims (8)

  1. Interlayer insulating film and The system comprises a plurality of resistive films disposed on the interlayer insulating film, Each of the plurality of resistive films extends in a first direction along the upper surface of the interlayer insulating film in a plan view, The plurality of resistive films are arranged in a plan view along the upper surface of the interlayer insulating film and spaced apart in a second direction perpendicular to the first direction. The aforementioned plurality of resistive films are divided into a first group, a second group, and a third group. The first group is located between the second group and the third group in the second direction. The second width variation of each of the multiple second resistive films belonging to the second group and the third width variation of each of the multiple third resistive films belonging to the third group are greater than the first width variation of each of the multiple first resistive films belonging to the first group. The first width variation is the difference between the reference width and the width of each of the plurality of first resistive films. The second width variation is the difference between the reference width and the width of each of the plurality of second resistive films. The third width variation is the difference between the reference width and the width of each of the plurality of third resistive films. The aforementioned reference width is the width of one of the plurality of resistive films located in the center in the second direction. The plurality of first resistive films are electrically connected to the first circuit group. At least a portion of the plurality of second resistive films and/or at least a portion of the plurality of third resistive films are electrically connected to a second circuit group different from the first circuit group. The first group of circuits includes at least one of an analog-to-digital converter circuit, a digital-to-analog converter circuit, a bandgap reference circuit, a high-frequency circuit, and an amplification circuit. The second group of circuits includes at least one of a circuit on which calibration is performed and a circuit on which a voltage is generated from a power supply voltage, wherein the semiconductor device.
  2. The semiconductor device according to claim 1, wherein the plurality of second resistive films and the plurality of third resistive films are electrically connected to the second circuit group.
  3. The semiconductor device according to claim 2, wherein the width of each of the plurality of second resistive films and the width of each of the plurality of third resistive films are smaller than the reference width.
  4. The semiconductor device according to claim 3, wherein, in the first direction, the length of each of the plurality of second resistive films is shorter than the length of each of the plurality of first resistive films.
  5. The semiconductor device according to claim 2, wherein the width of each of the plurality of second resistive films and the width of each of the plurality of third resistive films are greater than the reference width.
  6. The width of each of the plurality of second resistive films decreases as the distance from the first group increases in the second direction. The difference in width between two adjacent second resistive films in the plurality of second resistive films increases as the distance from the first group increases in the second direction. The width of each of the plurality of third resistive films decreases as the distance from the first group increases in the second direction. The semiconductor device according to claim 2, wherein the difference in width between two adjacent third resistive films among the plurality of third resistive films increases as the distance from the first group increases in the second direction.
  7. A portion of the plurality of second resistive films and a portion of the plurality of third resistive films are electrically connected to the second circuit group. The semiconductor device according to claim 1, wherein the remainder of the plurality of second resistive films and the remainder of the plurality of third resistive films are dummy resistive films.
  8. The semiconductor device according to claim 1, wherein each of the plurality of resistive films is formed of a material comprising at least one selected from the group consisting of silicon chromium, silicon chromium with carbon introduced, nickel chromium, titanium nitride, and tantalum nitride.

Description

This disclosure relates to semiconductor devices. The semiconductor device described in Japanese Patent Publication No. 2011-155192 (Patent Document 1) comprises an interlayer insulating film and a plurality of resistive films. The plurality of resistive films are arranged on the interlayer insulating film. Each of the plurality of resistive films extends along a first direction. The plurality of resistive films are spaced apart along a second direction perpendicular to the first direction. Japanese Patent Publication No. 2011-155192 This is a cross-sectional view of semiconductor device DEV1.This is a planar layout diagram of multiple resistive RF films in semiconductor device DEV1.This is a schematic block diagram of the semiconductor device DEV1.This is a manufacturing process diagram for the semiconductor device DEV1.This is a cross-sectional view illustrating the first wiring formation process S1.This is a cross-sectional view illustrating the first interlayer insulating film formation process S2.This is a cross-sectional view illustrating the first via hole formation process S3.This is a cross-sectional view illustrating the first via plug formation process S4.This is a cross-sectional view illustrating the resistive film formation process S5.This is a cross-sectional view illustrating the second interlayer insulating film formation process S6.This is a cross-sectional view illustrating the second via hole formation process S7.This is a cross-sectional view illustrating the second via plug formation step S8.This is a cross-sectional view illustrating the second wiring formation process S9.This is a planar layout diagram of the resistive RF in the semiconductor device DEV2.This is a planar layout diagram of the resistive RF film in semiconductor device DEV3.This is a planar layout diagram of the resistive RF in semiconductor device DEV4.This is a planar layout diagram of the resistive RF in semiconductor device DEV5.This is a planar layout diagram of a resistive RF in a modified example of semiconductor device DEV5. The embodiments of this disclosure will be described in detail with reference to the drawings. In the following drawings, the same or corresponding parts will be denoted by the same reference numerals, and redundant descriptions will not be repeated. (First Embodiment) A semiconductor device according to the first embodiment will be described. The semiconductor device according to the first embodiment will be referred to as semiconductor device DEV1. <Configuration of Semiconductor DEV1> The configuration of the semiconductor device DEV1 is described below. Figure 1 is a cross-sectional view of the semiconductor device DEV1. Figure 2 is a planar layout diagram of the resistive film RF in the semiconductor device DEV1. As shown in Figures 1 and 2, the semiconductor device DEV1 has a semiconductor substrate SUB and a plurality of interlayer insulating films ILDs. The semiconductor substrate SUB is formed of, for example, single-crystal silicon (Si). The plurality of interlayer insulating films ILDs are arranged on the semiconductor substrate SUB. Each of the plurality of interlayer insulating films ILDs is formed of, for example, silicon oxide ( SiO2 ). One of the plurality of interlayer insulating films ILDs is referred to as interlayer insulating film ILD1. The semiconductor device DEV1 has wiring WL1 and wiring WL2. Wiring WL1 and WL2 are arranged on an interlayer insulating film ILD1. Wiring WL1 and WL2 are formed of, for example, aluminum (Al) or an aluminum alloy. Barrier metal BM1 is placed between wiring WL1 and the interlayer insulating film ILD1, and between wiring WL2 and the interlayer insulating film ILD1. Barrier metal BM2 is placed on wiring WL1 and wiring WL2. Barrier metal BM1 and barrier metal BM2 are, for example, laminated films of titanium nitride (TiN) and titanium (Ti), respectively. One of the multiple interlayer insulating films (ILDs) is designated as ILD2. ILD2 is positioned on ILD1 so as to cover wirings WL1 and WL2. Via holes VH1 and VH2 are formed in ILD2. Via holes VH1 and VH2 penetrate ILD2 in the thickness direction. Parts of wirings WL1 and WL2 are exposed at the bottoms of via holes VH1 and VH2, respectively. The semiconductor device DEV1 has via plugs VP1 and VP2. Via plugs VP1 and VP2 are embedded in via holes VH1 and VH2, respectively. Via plugs VP1 and VP2 are made of, for example, tungsten (W). The lower end of via plug VP1 is electrically connected to wiring WL1. The lower end of via plug VP2 is electrically connected to wiring WL2. The semiconductor device DEV1 has multiple resistive films (RFs). The resistive films (RFs) are arranged on an interlayer insulating film (ILD2). The resistive films (RFs) are formed from conductive materials. Preferably, the resistive films (RFs) are formed from a material containing at least one selected from the group consisting of silicon chromium (SiCr), silicon chromium with carbon (C) introduced, nickel chromium (NiC