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JP-7855327-B2 - Semiconductor device having a conductive element formed above a dielectric layer and method for manufacturing the same

JP7855327B2JP 7855327 B2JP7855327 B2JP 7855327B2JP-7855327-B2

Inventors

  • イブラヒム カリル
  • ベルンハルト グロート
  • フマユーン カビール
  • ブルース マクレー グリーン

Assignees

  • エヌエックスピー ビー ヴィ

Dates

Publication Date
20260508
Application Date
20211027
Priority Date
20201231

Claims (18)

  1. A semiconductor substrate including the top surface and channel, A first dielectric layer disposed above the upper surface of the semiconductor substrate, Within a plurality of openings formed in the first dielectric layer, a first current-carrying electrode and a second current-carrying electrode are formed above the semiconductor substrate and are electrically coupled to the channel, A control electrode formed above the semiconductor substrate and positioned between the first current-carrying electrode and the second current-carrying electrode, and above the first dielectric layer, wherein the control electrode is electrically coupled to the channel, Between the control electrode and the second current-carrying electrode, a first conductive element is formed adjacent to the control electrode and above the first dielectric layer, A second dielectric layer is positioned above the control electrode and above the first conductive element, A second conductive element, Equipped with , The second conductive element is positioned in part above the second dielectric layer and above the first conductive element. A semiconductor device in which a portion of the second conductive element located between the control electrode and the first conductive element is below the upper surface of the first conductive element .
  2. The first conductive element is electrically coupled to the second conductive element. The semiconductor device according to claim 1.
  3. The first current-carrying electrode is configured as a source electrode, the second current-carrying electrode is configured as a drain electrode, and the control electrode is configured as a gate electrode. The semiconductor device according to claim 1.
  4. The first metal-insulating semiconductor region is formed below the first conductive element. The semiconductor device according to claim 3.
  5. The second metal-insulating semiconductor region is formed below the second conductive element and between the gate electrode and the first conductive element. The semiconductor device according to claim 4.
  6. A third metal-insulating semiconductor region is formed below the second conductive element and between the drain electrode and the first conductive element. The semiconductor device according to claim 5.
  7. The first conductive element is adjacent to the control electrode and is electrically insulated from the control electrode. The semiconductor device according to claim 1 .
  8. The first conductive element is configured as a first field plate, and the second conductive element is configured as a second field plate. The semiconductor device according to claim 6.
  9. The gate electrode and the first field plate are formed from the same material. The semiconductor device according to claim 8.
  10. The first field plate and the second field plate are at the same potential as the source electrode. The semiconductor device according to claim 8.
  11. The horizontal distance between the gate electrode and the first field plate is between 0.2 micrometers and 1 micrometer. The semiconductor device according to claim 8.
  12. The semiconductor substrate includes a group III nitride material. The semiconductor device according to claim 1.
  13. A semiconductor substrate including a gallium nitride layer, a top surface and a channel, A first dielectric layer disposed above the upper surface of the semiconductor substrate, An active region defined by an isolated region formed within the semiconductor substrate, Within the active region, in a plurality of openings formed in the first dielectric layer, a source electrode and a drain electrode formed above the semiconductor substrate, which are electrically coupled to the channel, A gate electrode formed above the semiconductor substrate and positioned between the source electrode and the drain electrode, and above the first dielectric layer, which is electrically coupled to the channel, A first field plate is formed between the gate electrode and the drain electrode, adjacent to the gate electrode, and above the first dielectric layer, wherein the first metal-insulating semiconductor region is formed below the first field plate. A second dielectric layer is disposed above the gate electrode and above the first field plate, A second field plate, the second field plate is partially positioned above the second dielectric layer and above the first field plate, a portion of the second field plate between the gate electrode and the first field plate is below the upper surface of the first field plate, a second metal-insulating semiconductor region is formed below the second field plate between the gate electrode and the first field plate, and a third metal-insulating semiconductor region is formed below the second field plate, adjacent to the first field plate and between the first field plate and the drain electrode, A gallium nitride heterojunction field-effect transistor device comprising the above features.
  14. Forming a semiconductor substrate including a gallium nitride layer, a top surface, and a channel, A first dielectric layer is formed above the upper surface of the semiconductor substrate, The method involves forming source electrodes and drain electrodes above the semiconductor substrate within a plurality of openings formed in the first dielectric layer, wherein the source electrodes and drain electrodes are electrically coupled to the channel. A gate electrode is formed above the semiconductor substrate, between the source electrode and the drain electrode, and above the first dielectric layer. A first field plate is formed between the gate electrode and the drain electrode, adjacent to the gate electrode, and above the first dielectric layer. A second dielectric layer is formed above the gate electrode and above the first field plate. To form a second field plate, Includes, The second field plate is formed in part above the second dielectric layer and above the first field plate. A method for manufacturing a gallium nitride heterojunction field-effect transistor device , wherein a portion of the second field plate located between the gate electrode and the first field plate is below the upper surface of the first field plate .
  15. The further includes forming an active region by defining an isolated region within the semiconductor substrate. The method according to claim 14.
  16. The formation of the gate electrode and the formation of the first field plate are performed using the same conductive layer. The method according to claim 14.
  17. Forming the source electrode and drain electrode includes forming ohmic contact regions that define the source region and drain region in the semiconductor substrate. The method according to claim 14.
  18. The second dielectric layer further includes forming a plurality of openings above the source electrode and the drain electrode. The method according to claim 14 .

Description

The embodiments of the subject matter described herein generally relate to semiconductor devices equipped with conductive elements and methods for manufacturing such devices. Semiconductor devices are applied to a wide variety of electronic components and systems. High-power, high-frequency transistors are used in radio frequency (RF) systems and power electronics systems. Gallium nitride (GaN) device technology is particularly well-suited to these RF power and power electronics applications due to its excellent electronic and thermal properties. In particular, the fast electron velocity and strong breakdown field strength of GaN make devices fabricated from this material ideal for RF power amplifiers and high-power switching applications. Field plates are used to reduce gate-drain feedback capacitance and increase the device breakdown voltage of high-frequency transistors. Therefore, semiconductors, especially GaN devices with field plates, are necessary. U.S. Patent No. 9,847,411U.S. Patent No. 10593619 This is a cross-sectional side view of an exemplary GaN heterojunction field-effect transistor (HFET) according to one embodiment.This is a cross-sectional side view of an exemplary GaN heterojunction field-effect transistor (HFET) according to one embodiment.This is a process flow diagram illustrating a method for manufacturing the GaN heterojunction field-effect transistor (HFET) device shown in Figures 1 and 2, according to one embodiment.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method.This is a cross-sectional side view of a manufacturing step for fabricating a GaN HFET device according to an embodiment of the manufacturing method. When considering the subject matter in conjunction with the drawings, a more complete understanding can be achieved by referring to the detailed descriptions and claims. Here, similar reference numbers refer to the same elements throughout the drawings. The following detailed description is, by its very nature, illustrative and not intended to limit the embodiments of the subject matter or the application and use of such embodiments. Where used herein, the terms “exemplary” and “example” mean “serving as an example, illustration, or illustration.” Implementations described herein as illustrative or illustrative should not necessarily be construed as being preferable or advantageous to other implementations. Furthermore, this description is not intended to be limited to the aforementioned technical fields, background art, or the explicit or implicit theories set forth in the following detailed description. In one embodiment, the semiconductor device may include a semiconductor substrate having a top surface and a channel, a first dielectric layer disposed above the top surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed above the semiconductor substrate within a plurality of openings formed in the first dielectric layer. Here, the first current-carrying electrode and the second current-carrying electrode are electrically coupled to the channel. A control electrode may be formed above the semiconductor substrate and disposed between the first current-carrying electrode and the second current-carrying electrode, and above the first dielectric layer. Here, according to one embodiment, the control electrode may be electrically coupled to the chann