JP-7855406-B2 - Method for manufacturing semiconductor memory devices

Inventors

• 蘆立 浩明
• 竹石 知之

Assignees

• キオクシア株式会社

Dates

Publication Date

20260508

Application Date

20220601

Claims (4)

1. A method for manufacturing a semiconductor memory device by bonding together a first substrate having an insulating layer and memory cells provided within the insulating layer, a second substrate having an insulating layer and memory cells provided within the insulating layer, and a third substrate having an insulating layer and control circuit provided within the insulating layer. The first substrate and the second substrate are bonded together via the insulating layers, and a trimming process is performed to remove the peripheral edges of the bonded first substrate and the second substrate, including the insulating layer between the first and second substrates, over a predetermined width, from the peripheral edge of the first substrate to the peripheral edge of the second substrate adjacent to the first substrate, and for the second substrate, a portion of the peripheral edge of the second substrate is removed over a predetermined width corresponding to the removal width of the first substrate, and then the remaining portion of the first substrate is removed by grinding to expose the insulating layer formed on the first substrate on the second substrate. The insulating layer of the third substrate is bonded to the exposed insulating layer. A method for manufacturing semiconductor memory devices.
2. After bonding the insulating layer of the third substrate to the exposed insulating layer, the remaining portion of the second substrate is removed, and a structure is obtained in which the insulating layer formed on the first substrate and the first memory cell array layer having the memory cells, and the insulating layer formed on the second substrate and the second memory cell array layer having the memory cells are laminated on the third substrate equipped with the control circuit. A method for manufacturing a semiconductor memory device according to claim 1 .
3. The first substrate has a first surface wiring layer on the surface of its insulating layer, and the second substrate has a second surface wiring layer on the surface of its insulating layer. When bonding the insulating layer of the first substrate and the insulating layer of the second substrate, the first surface wiring layer and the second surface wiring layer are aligned and bonded together. A method for manufacturing a semiconductor memory device according to claim 1 .
4. The memory cell is a memory cell having a laminate in which a plurality of electrode layers are stacked with a plurality of insulating layers in between, and the laminate is a laminate having a stepped structure in which the end positions of the plurality of electrode layers are shifted at each stacking position, When bonding the first substrate and the second substrate via the insulating layer, the inclined surface of the staircase structure is bonded toward the laminated interface of the bond between the first substrate and the second substrate. A method for manufacturing a semiconductor memory device according to claim 1 .

Description

Embodiments of the present invention relate to a method for manufacturing a semiconductor memory device. NAND flash memory with a bonded structure, where memory cells are stacked three-dimensionally, is known. U.S. Patent Application Publication No. 2018/0261623 A schematic cross-sectional view of a semiconductor memory device according to the first embodiment.A schematic perspective view of a semiconductor memory device according to the first embodiment.A schematic partial cross-sectional view of a semiconductor memory device according to the first embodiment.A schematic partial cross-sectional view showing an enlarged portion of a semiconductor memory device according to the first embodiment.A plan view showing an example of a semiconductor wafer used when manufacturing a semiconductor memory device according to the first embodiment.A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment.A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment.A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment.This is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment, and is a schematic cross-sectional view partially enlarged from the state shown in Figure 6.This is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment.This is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment, and is a schematic cross-sectional view partially enlarged from the state shown in Figure 9.A schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for comparative examples.A schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for comparative examples.A schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for comparative examples.This is a schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for a comparative example, and is a partially enlarged schematic cross-sectional view of a state preceding the state shown in Figure 12.This is a schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for a comparative example, and is a partially enlarged schematic cross-sectional view of the state one step further from the state shown in Figure 12.This is a schematic cross-sectional view showing an example of a semiconductor memory device manufacturing method for a comparative example, and is a partially enlarged schematic cross-sectional view of the state one step further from the state shown in Figure 14. "First Embodiment" The semiconductor memory device according to the first embodiment will be described below with reference to the drawings. In the following description, components having the same or similar function are denoted by the same reference numeral. Duplication of these components may be omitted. In this specification, “connection” includes not only physical connections but also electrical connections. In this specification, “provided on a substrate” includes cases where at least a portion of the object is formed inside the substrate or where at least a portion of the object is formed on the substrate. (First Embodiment) Figure 1 is a schematic cross-sectional view of a semiconductor memory device according to the first embodiment. The semiconductor memory device SMD of the first embodiment has a structure in which a control circuit layer 100, which has a control circuit for controlling the writing, erasing, and reading of data to memory cells provided on a substrate 1, and a first memory cell array layer 200, which includes a plurality of first memory cells arranged in three dimensions, are joined and laminated facing each other. Furthermore, the first memory cell array layer 200 and a second memory cell array layer 300, which includes a plurality of second memory cells arranged in three dimensions, are joined and laminated facing each other. To explain further, the semiconductor memory device SMD has a structure in which the control circuit layer 100, the first memory cell array layer 200, and the second memory cell array layer 300 are stacked on a substrate 1 in the thickness direction of the substrate 1. First, the first memory cell array layer 200 will be described. The first memory cell array layer 200 has a first surface (bottom surface) Sa1 and a second surface (top surface) Sa2 opposite to the first surface in Figure 1, and has a three-dimensi