JP-7855407-B2 - Semiconductor device and method for manufacturing the same

JP7855407B2JP 7855407 B2JP7855407 B2JP 7855407B2JP-7855407-B2

Inventors

蘆立浩明
加藤久詞
竹石知之

Assignees

キオクシア株式会社

Dates

Publication Date: 20260508
Application Date: 20220601

Claims (18)

First substrate and A first insulating film provided on the first substrate, A first pad provided within the first insulating film, A second insulating film provided on the first insulating film, A second pad provided within the second insulating film, positioned on the first pad, and in contact with the first pad, A third pad is provided within the second insulating film and positioned above the second pad, A third insulating film provided on the second insulating film, The third insulating film is provided within the third pad, and the fourth pad is positioned on the third pad and in contact with the third pad, The shapes of the first pad and the second pad in a plan view are the same, and the shapes of the third pad and the fourth pad in a plan view are the same. The shapes of the third and fourth pads in plan view differ from the shapes of the first and second pads in plan view . The sizes of the third and fourth pads in a plan view are larger than the sizes of the first and second pads in a plan view. The thickness of the third and fourth pads is the same as the thickness of the first and second pads. Semiconductor equipment.
The first memory cell array provided within the second insulating film, A second memory cell array provided within the third insulating film, The semiconductor device according to claim 1, further comprising:
The semiconductor device according to claim 2 , further comprising a circuit provided within the first insulating film for controlling the first and second memory cell arrays.
The upper surface of the first insulating film or the lower surface of the second insulating film is formed of the first insulating material. The semiconductor device according to claim 1, wherein the upper surface of the second insulating film or the lower surface of the third insulating film is formed of a second insulating material different from the first insulating material.
One of the first and second insulating materials comprises silicon and oxygen. The other of the first and second insulating materials comprises silicon, carbon, and nitrogen. The semiconductor device according to claim 4 .
First substrate and A first insulating film provided on the first substrate, A first metal layer provided within the first insulating film, A second insulating film provided on the first insulating film, A second metal layer provided within the second insulating film, positioned on the first metal layer, and in contact with the first metal layer, A third metal layer is provided within the second insulating film and positioned above the second metal layer, A third insulating film provided on the second insulating film, The third insulating film is provided within the third metal layer, which is arranged on the third metal layer and in contact with the third metal layer, and comprises a fourth metal layer. The first, second, third, or fourth metal layer is a plug provided on the surface of the wiring. The shapes of the first and second metal layers in a plan view are the same, and the shapes of the third and fourth metal layers in a plan view are the same. The shapes of the third and fourth metal layers in plan view differ from the shapes of the first and second metal layers in plan view. The sizes of the third and fourth metal layers in a plan view are larger than the sizes of the first and second metal layers in a plan view. The thicknesses of the third and fourth metal layers are the same as the thicknesses of the first and second metal layers. Semiconductor equipment.
One of the first and second metal layers, or one of the third and fourth metal layers, is a plug provided on the surface of the wiring. The other of the first and second metal layers, or the other of the third and fourth metal layers, is a pad provided on the surface of the wiring via a plug. The semiconductor device according to claim 6 .
One of the first and second metal layers, or one of the third and fourth metal layers, is a plug provided on the surface of the wiring. The other of the first and second metal layers, or the other of the third and fourth metal layers, is a plug provided on the surface of the wiring. The semiconductor device according to claim 6 .
The first memory cell array provided within the second insulating film, A second memory cell array provided within the third insulating film, The semiconductor device according to claim 6 , further comprising:
The semiconductor device according to claim 9 , further comprising a circuit provided within the first insulating film for controlling the first and second memory cell arrays.
A first insulating film is formed on the first substrate. A first metal layer is formed within the first insulating film. A second insulating film is formed on the second substrate. A second metal layer and a third metal layer are formed within the second insulating film. A third insulating film is formed on the third substrate. A fourth metal layer is formed within the third insulating film. The first insulating film and the second insulating film are bonded together so that the first metal layer and the second metal layer are in contact, and after bonding the first insulating film and the second insulating film, at least the first and second metal layers are annealed at a first temperature. The second insulating film and the third insulating film are bonded together such that the third metal layer and the fourth metal layer are in contact, and after bonding the second insulating film and the third insulating film, at least the third and fourth metal layers are annealed at a second temperature. This includes, A method for manufacturing a semiconductor device, wherein the second temperature is different from the first temperature.
The method for manufacturing a semiconductor device according to claim 11 , wherein the bonding of the second insulating film and the third insulating film is performed after annealing at a first temperature.
The method for manufacturing a semiconductor device according to claim 11 , wherein the bonding of the first insulating film and the second insulating film is performed after annealing at the second temperature.
A first memory cell array is formed on the second substrate. A second memory cell array is formed on the third substrate. A method for manufacturing a semiconductor device according to claim 11 , further comprising the following:
The method for manufacturing a semiconductor device according to claim 14 , further comprising forming circuits for controlling the first and second memory cell arrays on the first substrate.
The method for manufacturing a semiconductor device according to claim 15 , wherein the second temperature is higher than the first temperature.
The method for manufacturing a semiconductor device according to claim 11 , wherein the first, second, third, and fourth metal layers are, respectively, the first, second, third, and fourth pads.
The method for manufacturing a semiconductor device according to claim 11 , wherein the first, second, third, or fourth metal layer is a plug provided on the surface of the wiring.

Description

Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. When manufacturing semiconductor devices by bonding three or more substrates together with an interlayer insulating film, a key issue is how to form the bonding pads within the interlayer insulating film. Japanese Patent Publication No. 2018-152419 This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.This is a cross-sectional view showing the structure of the memory cell arrays 26 and 36 of the first embodiment.This is a cross-sectional view (1/5) showing a method for manufacturing a semiconductor device according to the first embodiment.This is a cross-sectional view (2/5) showing a method for manufacturing a semiconductor device according to the first embodiment.This is a cross-sectional view (3/5) showing a method for manufacturing a semiconductor device according to the first embodiment.This is a cross-sectional view (4/5) showing a method for manufacturing a semiconductor device according to the first embodiment.This is a cross-sectional view (5/5) showing a method for manufacturing a semiconductor device according to the first embodiment.This is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment.This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.This is a plan view showing a first example of the metal pads 17, 22, 29, and 32 of the first embodiment.This is a plan view showing a second example of the metal pads 17, 22, 29, and 32 of the first embodiment.This is a plan view showing a third example of the metal pads 17, 22, 29, and 32 of the first embodiment.This is a cross-sectional view showing a fourth example of the metal pads 17, 22, 29, and 32 of the first embodiment.This is a cross-sectional view (1/2) illustrating the advantages of the semiconductor device of the first embodiment.This is a cross-sectional view (2/2) illustrating the advantages of the semiconductor device of the first embodiment.This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.This is a cross-sectional view for comparing the semiconductor device of the second embodiment with the semiconductor device of the comparative example.This is a cross-sectional view showing the structure of a semiconductor device of the first modified example of the second embodiment.This is a cross-sectional view showing the structure of a semiconductor device according to the second to fourth modified examples of the second embodiment.This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment.This is a cross-sectional view showing a modified example of the third embodiment for the manufacturing method of a semiconductor device. The embodiments of the present invention will be described below with reference to the drawings. In Figures 1 to 21, identical components are denoted by the same reference numerals, and redundant descriptions are omitted. (First Embodiment) Figure 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment. The semiconductor device in Figure 1 is, for example, a three-dimensional memory in which a circuit chip 1, an array chip 2, and an array chip 3 are bonded together. Figure 1 shows the bonding surface S1 between circuit chip 1 and array chip 2, and the bonding surface S2 between array chip 2 and array chip 3. The circuit chip 1 comprises a substrate 11, multiple transistors 12, an interlayer insulating film 13, multiple contact plugs 14, multiple wirings 15, multiple via plugs 16, and multiple metal pads 17. Each transistor 12 comprises a gate insulating film 12a, a gate electrode 12b, a diffusion layer 12c, and a diffusion layer 12d. The substrate 11 is an example of a first substrate, and the interlayer insulating film 13 is an example of a first insulating film. The metal pads 17 are examples of a first pad and a first metal layer. The array chip 2 comprises an interlayer insulating film 21, a plurality of metal pads 22, a plurality of via plugs 23, a plurality of wirings 24, a plurality of via plugs 25, a plurality of memory cell arrays 26, a plurality of wirings 27, a plurality of via plugs 28, and a plurality of metal pads 29. The interlayer insulating film 21 is an example of a second insulating film, and the metal pads 22 are examples of second pads and a second metal layer. The memory cell array 26 is an example of a first memory cell array, and the metal pads 29 are examples of third pads and a third metal layer. The array chip 3 comprises an interlayer insulating film 31, a plurality of metal pads 32, a plurality of via plugs 33, a plurality of wirings 34, a plurality of via plugs 35, a plurality of memory cell arrays 36, a plurality of wirings 37, a plurality o