JP-7855425-B2 - Pattern formation method, template manufacturing method, and semiconductor device manufacturing method

Inventors

• 寺山 正敏

Assignees

• キオクシア株式会社

Dates

Publication Date

20260508

Application Date

20220622

Claims (7)

1. A first pattern is formed on the side of the second layer provided on the first layer that is opposite to the first layer, comprising a first inclined portion and a plurality of first recesses that expose a part of the first layer provided in the first inclined portion. The method includes performing a first etching using the second layer as a mask to remove the first layer exposed by the plurality of first recesses and a part of the second layer , thereby forming a second pattern comprising a second inclined portion on which the first pattern is transferred and a plurality of second recesses provided in the second inclined portion , Forming the plurality of first recesses in the first pattern is A second resin layer is formed on the second layer having the first inclined portion, exposing a portion of the second layer and having a plurality of recesses of different depths. Using the second resin layer as a mask, the second layer exposed by the plurality of recesses is removed. A pattern formation method that includes the following.
2. Forming the two patterns described above is The first layer, which is exposed by the removal of the second layer by the first etching, is removed. The pattern forming method according to claim 1, further comprising the following:
3. Forming the two patterns mentioned above is The first etching is stopped before the second layer at the lowest position of the first inclined portion is removed by the first etching , The second etching process is performed until the second layer at the lowest position of the first inclined portion is removed and the first layer is exposed . The pattern forming method according to claim 1 , further comprising repeating the first etching and the second etching .
4. The pattern forming method according to claim 3, wherein the first pattern is determined by one or more of the following: the processing speed of the first layer and the second layer in the first etching, the arrangement of the second pattern, the angle between the bottom surface of the first layer and the second inclined portion of the second pattern, the height of the second pattern, the depth of the second pattern, and the amount of processing of the second layer in the second etching.
5. Forming the first inclined portion of the first pattern is A first resin layer having an inclination is formed on the second layer. The inclination is transferred to the second layer to form the first inclined portion. A pattern forming method according to claim 1 , including the following:
6. A first pattern is formed on the surface of a first layer provided on a substrate that is opposite to the substrate, the first pattern comprising a first inclined portion and a plurality of first recesses that expose a part of the substrate provided in the first inclined portion. The method includes performing a first etching using the first layer as a mask to remove the substrate exposed by the plurality of first recesses and a part of the first layer , thereby forming a second pattern on the substrate comprising a second inclined portion on which the first pattern is transferred and a plurality of second recesses provided in the second inclined portion , Forming the plurality of first recesses in the first pattern is A second resin layer is formed on the first layer having the first inclined portion, exposing a portion of the first layer and having a plurality of recesses of different depths. Using the second resin layer as a mask, the first layer exposed by the plurality of recesses is removed. A method for manufacturing templates, including the following.
7. The method for forming the first pattern includes: forming a first pattern on a substrate on the side of the first layer opposite to the substrate, comprising a first inclined portion and a plurality of first recesses that expose a portion of the substrate provided in the first inclined portion; performing a first etching using the first layer as a mask to remove the substrate exposed by the plurality of first recesses and a portion of the first layer , thereby forming a second pattern on the substrate comprising a second inclined portion and a plurality of second recesses provided in the second inclined portion , wherein forming the plurality of first recesses of the first pattern involves forming a second resin layer on the first layer comprising the first inclined portion, exposing a portion of the first layer and having a plurality of recesses of different depths, and using the second resin layer as a mask to remove the first layer exposed by the plurality of recesses; and preparing a template manufactured using such a pattern forming method and a laminate on a semiconductor substrate in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. An insulator is applied to cover the laminate, By pressing the template, a first hole is formed in the insulator that exposes one of the plurality of conductive layers, and a second hole is formed that has a different depth from the first hole and exposes another of the plurality of conductive layers. To form a conductor in the first hole and the second hole, A method for manufacturing a semiconductor device containing [a specific component].

Description

Embodiments of this disclosure relate to a pattern formation method, a template manufacturing method, and a semiconductor device manufacturing method. As a semiconductor device, semiconductor packages using NAND flash memory are well known. To increase the capacity of such NAND flash memory, 3D NAND flash memory, which employs a configuration of stacked memory cells, has been put into practical use. Multiple conductive layers connected to each memory cell are stacked on a substrate and connected to drive circuits, etc. The contacts connecting each of the multiple conductive layers stacked on the substrate have multi-gradation patterns in the stacking direction. Therefore, nanoimprint lithography, which involves imprinting a multi-gradation template onto the resist to form the pattern, is useful. Japanese Patent Publication No. 2020-120023U.S. Patent Application Publication No. 2019/0074181U.S. Patent No. 10274822U.S. Patent Application Publication No. 2017/0263445U.S. Patent Application Publication No. 2018/0224740U.S. Patent No. 9,147,687 This is a cross-sectional view showing the configuration of a template pattern according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a perspective view showing the overall configuration of a semiconductor device according to one embodiment.This is a perspective view showing the configuration of the memory cell region (MCR) and the contact region (HUR) of a semiconductor device according to one embodiment.This is a cross-sectional view showing the configuration of a stacked wiring structure of a semiconductor device according to one embodiment.This is a cross-sectional view showing a method for manufacturing a stacked wiring structure of a semiconductor device according to one embodiment.This is a cross-sectional view showing a method for manufacturing a stacked wiring structure of a semiconductor device according to one embodiment.This is a cross-sectional view showing a method for manufacturing a stacked wiring structure of a semiconductor device according to one embodiment.This is a cross-sectional view showing a method for manufacturing a stacked wiring structure of a semiconductor device according to one embodiment.This is a cross-sectional view showing the configuration of a template pattern according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing the configuration of a stacked wiring structure according to one embodiment.This is a cross-sectional view showing a method for manufacturing a stacked wiring structure of a semiconductor device according to one embodiment.This is a cross-sectional view showing a method for manufacturing a stacked wiring structure of a semiconductor device according to one embodiment.This is a cross-sectional view showing a method for manufacturing a stacked wiring structure of a semiconductor device according to one embodiment.This is a cross-sectional view showing a method for manufacturing a stacked wiring structure of a semiconductor device according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern formation method according to one embodiment.This is a cross-sectional view showing a template pattern