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JP-7855459-B2 - Wiring board

JP7855459B2JP 7855459 B2JP7855459 B2JP 7855459B2JP-7855459-B2

Inventors

  • 古谷 俊樹

Assignees

  • イビデン株式会社

Dates

Publication Date
20260508
Application Date
20220829

Claims (12)

  1. Multiple stacked insulating layers, A plurality of conductive layers stacked via any one of the aforementioned plurality of insulating layers, It includes, A wiring substrate having a first surface as an outer surface intersecting the stacking direction of the plurality of insulating layers, The wiring board further comprises a first region and a second region adjacent to each other, each composed of a portion of the plurality of insulating layers and a portion of the plurality of conductive layers. The plurality of conductive layers are, A first conductor layer formed across the first and second regions, The present invention includes a second conductor layer formed only within the second region and alternately stacked with the first conductor layer in the second region, with any of the plurality of insulating layers in between, The plurality of insulating layers include a first insulating layer that contacts the first conductor layer on its upper surface facing the first surface, and a second insulating layer that contacts the second conductor layer on its upper surface facing the first surface. The first insulating layer and the second insulating layer have different surface roughness levels on their upper surfaces facing the first surface.
  2. A wiring board according to claim 1, The second insulating layer comprises an insulating resin and granular inorganic fillers added to the insulating resin. The maximum particle size of the inorganic filler is smaller than the maximum particle size of the inorganic filler in the first insulating layer.
  3. The wiring board according to claim 1, wherein the surface roughness of the upper surface of the second insulating layer is lower than the surface roughness of the upper surface of the first insulating layer.
  4. A wiring board according to claim 1, The relative permittivity of the second insulating layer is lower than that of the first insulating layer. The dielectric loss tangent of the second insulating layer is smaller than the dielectric loss tangent of the first insulating layer.
  5. A wiring board according to claim 1, The second conductor layer includes a plurality of wiring patterns, The minimum wiring width of the plurality of wiring patterns is smaller than the minimum wiring width of the wiring pattern included in the first conductor layer. The minimum distance between each of the plurality of wiring patterns is smaller than the minimum distance between the wiring patterns included in the first conductor layer.
  6. A wiring board according to claim 5, The minimum wiring width of the aforementioned plurality of wiring patterns is 5 μm or less. The minimum distance between each of the aforementioned multiple wiring patterns is 7 μm or less.
  7. The wiring board according to claim 5, wherein the aspect ratio of each of the plurality of wiring patterns is 2.0 or more and 4.0 or less.
  8. The wiring board according to claim 1, wherein the surface of the second conductor layer facing the first surface is a polished surface.
  9. A wiring board according to claim 1, The first conductor layer and the second conductor layer are each composed of a lower layer directly formed on the upper surface of the first insulating layer or the upper surface of the second insulating layer, and an upper layer formed on the lower layer and consisting of a plating film. The lower layer constituting the second conductor layer is made of a sputtered film.
  10. The wiring board according to claim 9, wherein the lower layer constituting the first conductor layer is made of an electroless plating film.
  11. A wiring board according to claim 1, The first surface has two or more component mounting areas, each of which a component is placed. The second region, in a plan view, spans between at least two of the two or more component mounting regions and partially overlaps with each of the at least two regions.
  12. The wiring board according to claim 1, wherein in the first region, any two of the plurality of insulating layers are interposed between adjacent first conductor layers in the stacking direction of the plurality of insulating layers.

Description

This invention relates to a wiring board. Patent Document 1 discloses a wiring substrate comprising a first wiring member consisting of insulating layers and wiring layers laminated on each surface of a core layer, and a second wiring member having a thinner interlayer thickness and higher wiring density than the first wiring member, and laminated on the outside of the first wiring member. Japanese Patent Publication No. 2014-225631 A cross-sectional view showing an example of a wiring board according to one embodiment of the present invention.A plan view showing an example of a wiring board in a plan view, as shown in Figure 1.Enlarged view of part III in Figure 1.An enlarged view of an example of part IV in Figure 3.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment.A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. A wiring board according to one embodiment of the present invention will be described with reference to the drawings. Figure 1 shows a cross-sectional view of a wiring board 1, which is an example of a wiring board of this embodiment. Figure 2 shows an example of a plan view of the wiring board 1 from the first surface FA side. Figure 1 is a cross-sectional view taken along line I-I in Figure 2. "Plan view" means viewing the object from a line of sight along the thickness direction of the wiring board 1. Furthermore, Figure 3 shows an enlarged view of part III in Figure 1. Note that wiring board 1 is merely an example of a wiring board of the embodiment. For example, the number of conductor layers and insulating layers included in the wiring board of the embodiment is not limited to the number of conductor layers and insulating layers included in the wiring board 1 in Figure 1. Also, in the drawings referenced in the following description, certain parts may be enlarged to facilitate understanding of the disclosed embodiment, and the size and length of each component may not be depicted in the exact proportions relative to each other. The wiring board 1 shown in Figure 1 includes a core substrate 100 having two main surfaces (first main surface F1 and second main surface F2) that are substantially perpendicular to the thickness direction of the wiring board 1. The core substrate 100 includes an insulating layer 101, conductor layers 102 formed on both sides of the insulating layer 101, and through-hole conductors 103 connecting the two conductor layers 102. The first main surface F1 and the second main surface F2 are formed by the exposed portions of the two surfaces of the insulating layer 101 that are substantially perpendicular to the thickness direction of the wiring board 1. The interior of the through-hole conductors 103 is filled with a resin body 103i containing epoxy resin or the like. The wiring board 1 further includes a first build-up section 10 and a second build-up section 20, each composed of a portion of multiple insulating layers and multiple conductive layers sequentially formed and laminated on each main surface of the core substrate 100 from the core substrate 100 side. The wiring board 1 has a first surface FA as its outer surface (outermost surface) intersecting the lamination direction of the multiple insulating layers laminated in the thickness direction of the wiring board 1, and a second surface FB which is the outer surface opposite the first surface FA. In the example in Figure 1, the first surface FA and the second surface FB are substantially p