JP-7855581-B2 - System and design method for a clock synchronizer for an integrated, aggregated, and distributed unit.

JP7855581B2JP 7855581 B2JP7855581 B2JP 7855581B2JP-7855581-B2

Inventors

ナレンデル・クマール
シャクティ・シン
アムリシュ・バンサル
ブリジェシュ・シャー
バジンデール・パル・シン
セルヴァクマール

Assignees

ジェイアイオー・プラットフォームズ・リミテッド

Dates

Publication Date: 20260508
Application Date: 20230324
Priority Date: 20220331

Claims (10)

A synchronizer system in an integrated aggregated distributed unit (CCDU) system, It comprises a single integrated board, and the single integrated board is It also features a chassis equipped with a clock synchronizer module, The clock synchronizer module, A boundary clock (BC) having one or more synchronization blocks, One or more high-precision timing protocol (PTP) engines, A primary synchronizer module using a Global Positioning System (GPS) signal , further comprising a primary synchronizer module which is a primary source of clock operation supporting holdover for a predetermined time interval, The BC, the one or more PTP engines, and the primary synchronizer module work together to achieve synchronization with one or more components of the CCDU system . A synchronizer system in which one or more PTP engines are secondary sources of synchronization, and the one or more PTP engines are automatically activated if the primary synchronizer module fails to lock and generate a clock signal .
The system according to claim 1, wherein the holdover mode of the clock synchronizer module is activated if both the primary synchronizer module and the one or more PTP engines fail to lock the clock signal .
The system according to claim 1 , wherein the clock synchronizer module is configured to make a determination that allows synchronization in one or more PTP or holdover modes to take precedence over synchronization in the primary synchronizer module , without manual intervention.
The system according to claim 1, wherein the clock synchronizer module synchronizes the synchronizer system on a single board and further synchronizes one or more external components associated with the synchronizer system .
The system according to claim 1, wherein the clock and synchronization modules mounted on the clock synchronizer module further include an ultra-low noise clock generation phase-locked loop (PLL), a programmable oscillator, and a system synchronizer.
A method for facilitating synchronization of a Integrated Concentrated Distributed Unit (CCDU) system using a synchronizer system, The steps include : generating a clock signal of a predetermined frequency using a primary synchronizer module that utilizes the Global Positioning System (GPS) signal ; The steps include locking the clock signal generated by the primary synchronizer module at the predetermined frequency, A step of generating a predetermined high-precision time protocol (PTP) packet using a predetermined reference clock and phase information obtained from the clock signal, wherein the one or more PTP engines are secondary synchronizer modules; If the primary synchronizer module fails to lock and generate the clock signal, the step of locking the clock signal with one or more PTP engines, wherein the secondary synchronizer module acts as a slave; A method comprising the steps of: generating a second clock signal of a second predetermined frequency using a boundary clock (BC) to provide the second clock signal for synchronizing one or more components of the CCDU system.
The method according to claim 6 , comprising the step of reading one or more NMEA (National Marine Electronics Association) packets within a predetermined time range via the GPS communication channel based on the generated clock signal.
The method according to claim 6 , further comprising the step of providing the plurality of clock signals by one or more PTP engines by recovering the plurality of clock signals from a backhaul network.
The method according to claim 6 , further comprising the step of entering holdover mode when both the primary synchronizer module and the one or more PTP engines fail to lock the clock signal .
In the processor, A primary synchronizer module using the Global Positioning System (GPS) signal generates a clock signal of a predetermined frequency . The clock signal generated by the primary synchronizer module is locked at the predetermined frequency. One or more high-precision timing protocol (PTP) engines generate predefined high-precision timing protocol (PTP) packets using a predefined reference clock and phase information obtained from the clock signal, and the one or more PTP engines are secondary synchronizer modules. If the primary synchronizer module fails to lock and generate the clock signal, one or more PTP engines will lock the clock signal, and the secondary synchronizer module will act as a slave. A non-temporary computer-readable medium including a processor-executable instruction that causes a boundary clock (BC) to generate a second clock signal of a second predetermined frequency, thereby providing the second clock signal to synchronize one or more components of an integrated aggregated distributed unit (CCDU) system.

Description

Embodiments of this disclosure generally relate to basic applications for telecommunications. More specifically, this disclosure relates to the design of a clock synchronizer for an integrated aggregated distributed unit (CCDU). The following description of related technology is intended to provide background information relevant to the field of this disclosure. This section may include certain aspects of technology that may relate to various features of this disclosure. However, it should be understood that this section is intended solely to enhance the reader's understanding of this disclosure and not to be used as an endorsement of prior art. Fifth-generation (5G) technology is expected to fundamentally change the role that telecommunications technology plays in general industry and society. gNodeB is a 3GPP® compliant implementation of a 5G-NR base station. As shown in Figure 1, gNodeB consists of independent network functions that implement the 3GPP® compliant NR Radio Access Network (RAN) protocol, namely the Physical Layer (PHY), Media Access Control Layer (MAC), Radio Link Control (RLC), Packet Data Convergence Protocol (PDCP), Service Data Adaptive Protocol (SDAP), Radio Resource Control (RRC), and Network Real-Time Analytics Platform (NRAP). gNB further incorporates three functional modules, CU, DU, and Radio Unit (RU), which can be deployed in multiple combinations. They can operate together or independently and can be deployed on either physical resources (e.g., small cell chipsets) or virtual resources (e.g., dedicated COTS servers or shared cloud resources). While the CU provides support for higher layers of the protocol stack, such as SDAP, PDCP, and RRC, the DU provides support for lower layers of the protocol stack, such as Radio Link Control (RLC), Media Access Control (MAC), and the physical layer. In a 5G radio access network (RAN) architecture, the DU in the baseband unit (BBU) handles the real-time Layer 1 and Layer 2 scheduling functions of the 5G protocol stack layer, while the CU handles the non-real-time higher Layer 2 and Layer 3 functions of the 5G protocol stack layer. However, in existing architectures, the DU unit and CU unit are physically separated, requiring costly and complex methods and protocol support to split the gNB into DU and CU. If the CU and DU are integrated together, internal and external synchronization problems to the system can arise. Therefore, in this field, there is a need to realize the design of a clock synchronizer module that enables a compact CCDU that can overcome the shortcomings of existing prior art. This figure illustrates an exemplary network architecture in which the proposed system of this disclosure can be implemented in or together with embodiments of this disclosure.This figure illustrates an exemplary system architecture of an integrated aggregated distributed unit (CCDU) according to an embodiment of the present disclosure.This diagram illustrates existing representations of aggregate and distributed units in gNodeB.This figure illustrates an exemplary synchronizer system for CCDU according to an embodiment of the present disclosure.This flowchart illustrates an exemplary method of a synchronizer system according to an embodiment of the present disclosure.This figure illustrates an exemplary computer system that utilizes embodiments of the present invention, in or in conjunction with embodiments thereof, according to embodiments of the present disclosure. The above will become even clearer from the following more detailed description of the present invention. The following description includes various specific details for illustrative purposes to provide a complete understanding of the embodiments of this disclosure. However, it will become clear that embodiments of this disclosure can be implemented without these specific details. Some of the features described hereafter can be used independently of each other or in any combination with other features. Individual features may not address all of the issues discussed above, or may only address some of them. Some of the issues discussed above may not be fully addressed by any of the features described herein. The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the following description of exemplary embodiments will provide a description that enables the implementation of the exemplary embodiments for those skilled in the art. It should be understood that various modifications to the functions and arrangement of elements can be made without departing from the spirit and scope of the invention as described. To provide a complete understanding of this embodiment, specific details are given in the following description. However, those skilled in the art will understand that this embodiment can be implemented without these specific details. For example, to avoid obscuring this embodiment