JP-7855620-B2 - Display board and method for manufacturing the same, display device

Inventors

• 王 利忠
• ▲寧▼ 策
• 邸 云萍
• 童 彬彬
• ▲張▼ 震
• ▲張▼ 振宇
• 李 付▲強▼
• 徐 成福

Assignees

• 京東方科技集團股▲ふん▼有限公司

Dates

Publication Date

20260508

Application Date

20210629

Claims (20)

1. A display substrate comprising a display area and a non-display area located around the display area, wherein the display area includes an aperture area and a non-aperture area, The invention comprises a base substrate and a thin-film transistor provided on one side of the base substrate, wherein the thin-film transistor includes a gate, an active layer, source and drain electrodes, and an auxiliary film layer, the auxiliary film layer having a cutout region, and the orthographic projection of the cutout region on the base substrate covers at least partially the aperture region. The thin-film transistor includes a first thin-film transistor located in the display region, the first thin-film transistor includes a stacked first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source, the first active layer is provided so as to be closer to the base substrate than the first gate insulating layer, the first gate, the first interlayer dielectric layer, and the first source. The auxiliary film layer includes the first gate insulating layer and the first interlayer dielectric layer, A first drain is further provided on the side of the first interlayer dielectric layer away from the base substrate, and the first drain is provided in the same layer as the first source. A first transparent electrode layer is further provided on the side of the first drain closest to the base substrate, the first transparent electrode layer includes a first relay electrode, the first relay electrode is in contact with and connected to the first drain, and the first drain is connected to the drain contact region of the first active layer via via holes provided in the first interlayer dielectric layer and the first gate insulating layer, on a display substrate.
2. The display substrate according to claim 1, wherein the orthographic projection of the auxiliary film layer on the base substrate does not overlap with the aperture region.
3. The first thin-film transistor further includes a shielding layer and a second interlayer dielectric layer provided between the base substrate and the first active layer, wherein the first active layer is provided on the side of the second interlayer dielectric layer away from the base substrate. The display substrate according to claim 1, wherein the auxiliary film layer further comprises the second interlayer dielectric layer.
4. The thin-film transistor includes a first thin-film transistor located in the display region and a second thin-film transistor located in the non-display region, and the material of the first active layer of the first thin-film transistor includes a metal oxide. The second thin-film transistor includes a buffer layer, a second active layer, a second gate insulating layer, and a second gate, which are laminated on the base substrate, wherein the second active layer is positioned closer to the base substrate than the buffer layer, the second gate insulating layer, and the second gate, and the material of the second active layer includes polycrystalline silicon. The display substrate according to claim 1, wherein the auxiliary film layer includes the buffer layer and the second gate insulating layer, and the orthographic projection of the cutout region in the buffer layer and the second gate insulating layer on the base substrate covers the display region at least partially.
5. A first flat layer is formed on the side of the first thin-film transistor that is away from the base substrate. The display substrate according to claim 4, wherein at the edges of the buffer layer and the second gate insulating layer approaching the display area, the first flat layer forms a stepped portion, and the thickness of the stepped portion corresponding to the non-display area is smaller than the thickness of the stepped portion corresponding to the display area.
6. The first transparent electrode layer further includes a second relay electrode formed integrally with the first relay electrode, the second relay electrode being located within the non-aperture region. A second flat layer is provided on the side of the first transparent electrode layer away from the base substrate, and a first through-hole is provided in the second flat layer, and the first through-hole penetrates the second flat layer so as to expose the second relay electrode. A second transparent electrode layer, a third flat layer, and a pixel electrode layer are provided on the side of the second flat layer away from the base substrate, the second transparent electrode layer is provided closer to the base substrate than the third flat layer and the pixel electrode layer, the orthographic projection of the second transparent electrode layer on the base substrate covers the orthographic projection of the first through hole on the base substrate, the second transparent electrode layer is for connecting the pixel electrode layer and the second relay electrode, and the third flat layer is for flattening the first through hole, the display substrate according to claim 1.
7. A display substrate according to claim 1, wherein a second passivation layer and a third transparent electrode layer are laminated on the side of the first transparent electrode layer away from the base substrate, the second passivation layer is positioned closer to the base substrate than the third transparent electrode layer, the third transparent electrode layer is connected to a first fixed potential input terminal, and the orthographic projection of the third transparent electrode layer on the base substrate overlaps with the orthographic projection of the first transparent electrode layer on the base substrate.
8. A third passivation layer and data lines are laminated on the side of the third transparent electrode layer away from the base substrate, the third passivation layer is positioned closer to the base substrate than the data lines, the data lines are connected to the first source via via holes provided in the third passivation layer and the second passivation layer, the first source is connected to the source contact region of the first active layer via via holes provided in the first gate insulating layer and the first interlayer dielectric layer, and the orthographic projection of the data lines on the base substrate covers the orthographic projection of the first active layer, first source, and first drain on the base substrate, as described in claim 7.
9. The display substrate according to claim 1, wherein the material of the first active layer comprises a metal oxide, the first active layer includes a drain contact region, and the drain contact region is located within the opening region.
10. A display substrate according to claim 6, wherein a fourth passivation layer and a common electrode layer are laminated on the side of the pixel electrode layer away from the base substrate, the fourth passivation layer is provided so as to be closer to the base substrate than the common electrode layer, the common electrode layer includes a plurality of strip-shaped electrodes, and the material of the common electrode layer is metal.
11. The display substrate according to claim 1, wherein the display area further includes data lines and scan lines, the first source extends along a first direction to constitute the data lines, the first gate extends along a second direction intersecting the first direction to constitute the scan lines, and the orthographic projections of the data lines and scan lines on the base substrate each cover the orthographic projection of the channel area of the first active layer on the base substrate.
12. The display substrate according to claim 11, wherein the material of the first active layer comprises polycrystalline silicon, and the orthographic projection of the data lines on the base substrate covers the orthographic projection of the first active layer on the base substrate.
13. The display substrate according to claim 1, wherein the channel region of the first active layer includes a first channel region, a first resistive region, and a second channel region arranged sequentially along a first direction, the first gate includes a separately provided first subgate and a second subgate, the orthographic projection of the first subgate on the base substrate covers the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second subgate on the base substrate covers the orthographic projection of the second channel region on the base substrate.
14. The display substrate according to claim 3, wherein the orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the channel region of the first active layer on the base substrate.
15. The display substrate according to claim 14, wherein the display area further includes data lines and scan lines, and the orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the data lines and scan lines on the base substrate.
16. The display substrate according to claim 15, wherein the shielding layer is connected to the second fixed potential input terminal.
17. The display substrate according to claim 3, wherein the material of the shielding layer comprises at least one of molybdenum, aluminum, and silver.
18. A display device comprising a display board according to any one of claims 1 to 17.
19. A method for manufacturing a display substrate, which includes a display area and a non-display area located around the display area, wherein the display area includes an aperture area and a non-aperture area, The steps include preparing the base board and A thin-film transistor is manufactured on one side of the base substrate, comprising the steps of: providing a cutout region in the auxiliary film layer, and ensuring that the orthographic projection of the cutout region on the base substrate covers at least a portion of the aperture region; The thin-film transistor includes a first thin-film transistor located in the display region, the first thin-film transistor includes a stacked first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source, the first active layer is provided so as to be closer to the base substrate than the first gate insulating layer, the first gate, the first interlayer dielectric layer, and the first source. The auxiliary film layer includes the first gate insulating layer and the first interlayer dielectric layer, A first drain is further provided on the side of the first interlayer dielectric layer away from the base substrate, and the first drain is provided in the same layer as the first source. A method for manufacturing a display substrate, wherein a first transparent electrode layer is further provided on the side of the first drain closest to the base substrate, the first transparent electrode layer includes a first relay electrode, the first relay electrode is in contact with and connected to the first drain, and the first drain is connected to the drain contact region of the first active layer via via holes provided in the first interlayer dielectric layer and the first gate insulating layer.
20. The thin-film transistor includes a first thin-film transistor located in the display region, and the step of manufacturing the thin-film transistor on one side of the base substrate is: The manufacturing method according to claim 19, comprising the step of sequentially forming a first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source on one side of the base substrate within the display area to obtain the first thin-film transistor, wherein the auxiliary film layer includes the first gate insulating layer and the first interlayer dielectric layer.

Description

This invention relates to the field of display technology, and more particularly to a display substrate, a method for manufacturing the same, and a display device. With the increasing prevalence of high-resolution display products and the growing demand in the virtual reality (VR) market, the display effectiveness of high-resolution display products is gradually becoming a focus of research. Currently, high-resolution display products generally suffer from the problem of low light transmittance. This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention.This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention.This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention.This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention.This is a schematic diagram showing the planar structure of a display substrate provided in an embodiment of the present invention.This is a schematic diagram showing the planar structure of the first thin-film transistor provided in an embodiment of the present invention.This is a schematic diagram showing the cross-sectional structure of the first thin-film transistor provided in an embodiment of the present invention.This is a schematic diagram showing the planar structure of the shielding layer provided in an embodiment of the present invention.This is a schematic diagram showing the cross-sectional structure of a display substrate after the lamination of the buffer layer and active layer materials provided in the embodiment of the present invention has been completed.This is a schematic diagram showing the cross-sectional structure of a display substrate in which the second active layer and buffer layer provided in an embodiment of the present invention have been completed.This is a schematic diagram showing the cross-sectional structure of a display substrate with a second gate and shielding layer completed, as provided in an embodiment of the present invention.This is a schematic diagram showing the cross-sectional structure of a display substrate in which the lamination of the second interlayer dielectric material provided in an embodiment of the present invention has been completed.This is a schematic diagram showing the cross-sectional structure of a display substrate in which the second interlayer dielectric layer provided in an embodiment of the present invention has been completed.This is a schematic diagram showing the cross-sectional structure of a display substrate in which the first active layer provided in an embodiment of the present invention has been completed.This is a schematic diagram showing the cross-sectional structure of a display substrate in which the first gate insulating layer provided in an embodiment of the present invention has been completed.This is a schematic diagram showing the cross-sectional structure of a display board with a completed first gate, as provided in an embodiment of the present invention.This is a schematic diagram showing the cross-sectional structure of a display substrate in which the first source and the first interlayer dielectric layer provided in an embodiment of the present invention have been completed.This is a schematic diagram showing the cross-sectional structure of a display substrate in which the fourth flat layer, fourth transparent electrode layer, fifth flat layer, and pixel electrode layer provided in the embodiment of the present invention have been completed. The following describes the technical aspects of the embodiments of the present invention more clearly and completely, with reference to the accompanying drawings, in order to further clarify the purpose, technical proposal, and advantages of the embodiments of the present invention. Note that the embodiments described are merely a subset of the present invention, not all embodiments. All other embodiments obtained based on the embodiments of the present invention, without requiring any creative work from those skilled in the art, fall within the scope of the protection of the present invention. One embodiment of the present invention provides a display substrate, which, referring to Figures 1 to 4, includes a display area comprising an aperture region and a non-aperture region, and a non-display region located around the display area. Referring to Figures 1 to 4, the display substrate includes a base substrate 11 and a thin-film transistor provided on one side of the base substrate 11. The thin-film transistor includes a gate, an active layer, source and drain electrodes, and an auxiliary film layer 10. The auxiliary film layer 10 has a cutout region, and the orthographic projection of the cutout region on the base substrate 11 covers a