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JP-7855702-B2 - Codeword synchronization method, communication device, chip, and chip system

JP7855702B2JP 7855702 B2JP7855702 B2JP 7855702B2JP-7855702-B2

Inventors

  • 任 浩
  • 何 向
  • 王 心▲遠▼

Assignees

  • 華為技術有限公司

Dates

Publication Date
20260508
Application Date
20221209
Priority Date
20220130

Claims (20)

  1. A codeword synchronization method, wherein the method is Steps include entering a synchronized position determination state in response to a start signal, The step of selecting a candidate position in the received data sequence in the synchronization position determination state, The aforementioned synchronization position determination state includes a step, which includes a seventh codeword verification substate, After entering the seventh codeword verification phase, the process involves increasing the count value of the sixth codeword counter by E, After entering the seventh codeword verification substate, the step of increasing the count value of the fourth valid codeword counter by F in response to a test block that satisfies the verification conditions, wherein both E and F are integers greater than or equal to 1, and the test block is selected based on the candidate position, A codeword synchronization method comprising the steps of determining the candidate position as a synchronization position in the data sequence in response that the count value of the sixth codeword counter is less than or equal to a ninth threshold and the count value of the fourth effective codeword counter is equal to a tenth threshold, wherein E is equal to 1, the ninth threshold is the number of test blocks selected based on the candidate position, F is equal to 1, the tenth threshold is the number of test blocks that satisfy the verification condition, and the synchronization position indicates the starting position of a codeword in the data sequence.
  2. The aforementioned method, The method according to claim 1, further comprising the step of determining whether the test block satisfies the verification conditions based on the characteristic values of the test block.
  3. The method according to claim 2, wherein the aforementioned characteristic value includes a syndrome.
  4. The step of determining whether the test block satisfies the verification conditions based on the characteristic values of the test block is: The method according to claim 3 , further comprising the step of determining that the test block satisfies the verification condition based on the fact that the syndrome of the test block is a zero vector.
  5. The aforementioned method, The method according to claim 1, further comprising the step of re-entering the seventh codeword verification partial state in response that the count value of the sixth codeword counter is less than the ninth threshold and the count value of the fourth valid codeword counter is less than the tenth threshold, and verifying the next test block selected based on the candidate position.
  6. The aforementioned method, The method according to claim 1, further comprising the step of reselecting a candidate position in response that the count value of the sixth codeword counter is equal to the ninth threshold and the count value of the fourth valid codeword counter is less than the tenth threshold.
  7. The synchronization position determination state further includes a sixth counter reset partial state, and the method is The method according to claim 1, further comprising the step of setting an initial value for the sixth codeword counter and an initial value for the fourth effective codeword counter after entering the sixth counter reset partial state.
  8. The step of selecting a candidate position in the received data sequence in the aforementioned synchronization position determination state is: The method according to claim 1, comprising the step of selecting N observation bits from the data sequence and selecting the synchronization position from the positions of the N observation bits in the synchronization position determination state, wherein N is an integer of 1 or more.
  9. The synchronization position determination state further includes a fourth codeword verification substate, and the step of selecting a candidate position in the received data sequence in the synchronization position determination state is: After entering the fourth codeword verification phase, the process involves increasing the count value of the third codeword counter by M, After entering the fourth codeword verification substate, the step of increasing the count value of the first valid codeword counter by Q in response to a test block that satisfies the verification condition, wherein both M and Q are integers greater than or equal to 1, and the test block is selected based on the currently observed bit, In response to the count value of the third codeword counter being less than or equal to the fifth threshold and the count value of the first effective codeword counter being equal to the sixth threshold, the step of determining the position of the current observed bit as the candidate position, The method according to claim 8, including the method described in claim 8.
  10. The step of selecting a candidate position in the received data sequence in the aforementioned synchronization position determination state is: The method according to claim 9, further comprising the step of re-entering the fourth codeword verification partial state and verifying the next test block selected based on the currently observed bits, in response that the count value of the third codeword counter is less than the fifth threshold and the count value of the first effective codeword counter is less than the sixth threshold.
  11. The step of selecting a candidate position in the received data sequence in the aforementioned synchronization position determination state is: The method according to claim 9, further comprising the step of verifying the next observed bit selected from the data sequence in response that the count value of the third codeword counter is equal to the fifth threshold and the count value of the first effective codeword counter is less than the sixth threshold.
  12. The synchronization position determination state further includes a third counter reset partial state, and the method is The method according to claim 11, further comprising the step of setting an initial value for the third codeword counter and an initial value for the first effective codeword counter after entering the third counter reset partial state.
  13. The aforementioned synchronization position determination state further includes a third slip portion state, The step of verifying the next observed bit selected from the aforementioned data sequence is: The step of entering the third slipping state, After entering the third slip portion state, the step of slipping to the next observation bit, In response to slipping to the next observed bit, the third counter reset partial state is re-entered, and the next observed bit is verified. The method according to claim 12, including the method described in claim 12.
  14. The method according to claim 9, wherein the test block selected based on the current observed bit belongs to a first subsequence in the data sequence, and the test block selected based on the candidate position belongs to a second subsequence in the data sequence, the second subsequence being positioned after the first subsequence.
  15. The aforementioned method, In response to determining the synchronization position, the step is to enter a lock loss detection state, In the lock loss detection state, the steps include verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, re-entering the synchronization position determination state, The method according to claim 1, further comprising:
  16. The lock loss detection state includes a sixth codeword verification substate, In the lock loss detection state, the step of verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, returning to the synchronization position determination state, After entering the sixth codeword verification phase, the step is to increase the count value of the fifth codeword counter by 1, After entering the sixth codeword verification phase, the process includes the step of increasing the count value of the second invalid codeword counter by 1 in response to a codeword that does not satisfy the verification conditions, wherein the codeword is selected based on the synchronization position. The steps include: re-entering the synchronization position determination state in response to the count value of the fifth codeword counter being less than or equal to the target value and the count value of the second effective codeword counter being equal to the eighth threshold; The method according to claim 15, including the method described in claim 15.
  17. In the lock loss detection state, the step of verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, returning to the synchronization position determination state, The method according to claim 16, further comprising the step of performing the following verification on the synchronization position in response that the count value of the fifth codeword counter is equal to the target value and the count value of the second invalid codeword counter is less than an eighth threshold.
  18. In the lock loss detection state, the step of verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, returning to the synchronization position determination state, The method according to claim 16, further comprising the step of verifying the next codeword selected based on the synchronization position in response that the count value of the fifth codeword counter is less than the target value and the count value of the second invalid codeword counter is less than the eighth threshold.
  19. The lock loss detection state further includes a fifth counter reset partial state, and the method The method according to claim 16, further comprising the step of setting an initial value for the fifth codeword counter and an initial value for the second invalid codeword counter after entering the fifth counter reset partial state.
  20. The method according to claim 1, wherein the start signal includes a system reset signal, a system start signal, a data reception failure signal, or a resynchronization signal.

Description

This application claims priority to Chinese Patent Application No. 202210113601.8, titled "STATE MACHINE BASED BLOCK CODE SELF-SYNCHRONIZATION METHOD," filed on January 30, 2022, and Chinese Patent Application No. 202210520888.6, titled "CODEWORD SYNCHRONIZATION METHOD, COMMUNICATION DEVICE, CHIP, AND CHIP SYSTEM," filed on May 12, 2022, both of which are incorporated herein by reference in their entirety. This application relates to the field of communication technology, and more particularly to codeword synchronization methods, communication devices, chips, and chip systems. Currently, with the advancement of communication technology, channel loss and noise have become significant factors limiting data transmission speed and distance. Forward error correction (FEC) provides error correction protection to data in transmission, thereby increasing the data transmission speed and distance of the channel. FEC includes block codes, which include linear block codes and non-linear block codes. Because the encoding and decoding of linear block codes are simple, linear block codes are widely applied in the physical layer and media access control (MAC) sublayer of the data link layer within the Ethernet open system interconnection model (OSI). Error detection and correction functions in linear block codes must be implemented based on complete codewords. Therefore, codeword boundaries must be determined in the data sequence; that is, the start and end of complete codewords must be found. This process is called codeword synchronization or frame synchronization. Currently, synchronization solutions applicable to linear block codes are available in the industry. One example is the alignment marker (AM) synchronization solution used in the 802.3 standard 200/400 GE. In this solution, fixed AM sequences must be inserted at intervals of codewords of a specific length, and the receiver can perform codeword synchronization by identifying the AM sequences. However, the presence of AM sequences is equivalent to inserting additional data into the data stream transmitted by the transmitter, thus adding redundant information. This application provides a codeword synchronization method, a communication device, a chip, and a chip system, which enable codeword synchronization to be implemented without AM insertion, thereby saving transmission resources. This is a diagram illustrating the principle of a state machine according to an exemplary embodiment of this application.This is a diagram of a codeword and synchronization position according to an exemplary embodiment of the present application.This is a diagram illustrating an application scenario according to an exemplary embodiment of the present application.This is a diagram illustrating an application scenario according to an exemplary embodiment of the present application.This is a diagram illustrating an application scenario according to an exemplary embodiment of the present application.This is a diagram illustrating an application scenario according to an exemplary embodiment of the present application.This is a schematic logic diagram of codeword synchronization according to an exemplary embodiment of the present application.This is a flowchart of a method for implementing codeword synchronization based on a state machine, according to an exemplary embodiment of the present application.This is a state diagram for determining the synchronization position according to an exemplary embodiment of the present application.This is a state diagram of synchronization position determination and lock loss detection according to an exemplary embodiment of the present application.This is a state diagram illustrating the determination of a candidate position according to an exemplary embodiment of the present application.This is a state diagram illustrating the determination of a candidate position according to an exemplary embodiment of the present application.This is a state diagram illustrating the determination of a candidate position according to an exemplary embodiment of the present application.This is a state diagram showing the determination of whether to verify a candidate position according to an exemplary embodiment of the present application.This is a state diagram showing the determination of whether to verify a candidate position according to an exemplary embodiment of the present application.This is a state diagram of a lock loss detection process according to an exemplary embodiment of the present application.This is a state diagram of a lock loss detection process according to an exemplary embodiment of the present application.This is a state diagram illustrating the determination of a candidate position according to an exemplary embodiment of the present application.This is a schematic diagram of the structure of a codeword synchronization device according to an exemplary embodiment of the present application.This is a diagram showing the structure of a communication