JP-7855719-B2 - Phase-mode bit-addressable sensing register

Inventors

• ブラウン、アレクサンダー ルイス
• ニールセン、マックス イー．
• ドシュ、ダニエル ジョージ
• プレイム、カート
• ダイ、ハイタオ オー．
• ウォレス、チャールズ ライアン

Assignees

• ノースロップ グラマン システムズ コーポレーション

Dates

Publication Date

20260508

Application Date

20230331

Priority Date

20220504

Claims (10)

1. A reciprocal quantum logic (hereinafter referred to as RQL) integrated circuit (hereinafter referred to as IC), A phase mode shift register is provided, and the phase mode shift register is A first set of multiple Josephson transmission lines (hereinafter referred to as JTLs) arranged in series as a data path, A second set of multiple JTLs arranged in series as a logic clock path trunk, A plurality of phase-mode D flip-flops, each having a data input coupled to the data path and configured to receive input from the data path, a data output coupled to the data path and configured to provide output to the data path, and a logic clock input coupled to a branch of an individual logic clock path coupled to the logic clock path trunk, The first plurality of JTLs and the plurality of phase-mode D flip-flops in the data path are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of two first AC clock phases separated by approximately 180° from each other. The second plurality of JTLs in the logic clock path trunk are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of two second AC clock phases separated by approximately 180° from each other. The first two AC clock phases are different from the second two AC clock phases, RQL IC.
2. The first of the two AC clock phases is approximately 90° away from the first of the two AC clock phases. The RQL IC according to claim 1, wherein the second of the first two AC clock phases is separated by approximately 90° from the second of the second two AC clock phases.
3. The first of the two AC clock phases mentioned above has a phase of approximately 0°. The first of the two AC clock phases mentioned above has a phase of approximately 90°. The second of the two AC clock phases mentioned above is approximately 180°, The second of the two AC clock phases is approximately 270° or The first of the two AC clock phases mentioned above has a phase of approximately 0°. The first of the two AC clock phases mentioned above has a phase of approximately 90°. The second of the two AC clock phases mentioned above has a phase of approximately 180°. The RQL IC according to claim 2, wherein the second of the two first AC clock phases is approximately 270°.
4. The first of the two AC clock phases mentioned above has a phase of approximately 45°. The first of the two AC clock phases mentioned above has a phase of approximately 135°. The second of the two AC clock phases described above is approximately 225°, The second of the two AC clock phases is approximately 315° or The first of the two AC clock phases mentioned above has a phase of approximately 45°. The first of the two AC clock phases mentioned above has a phase of approximately 135°. The second of the two AC clock phases mentioned above has a phase of approximately 225°. The RQL IC according to claim 2, wherein the second of the two first AC clock phases is approximately 315°.
5. The RQL IC according to claim 1, wherein each of the plurality of phase-mode D flip-flops is transformer-coupled to the one or more AC clock resonators at different points along the one or more AC clock resonators.
6. The RQL IC according to claim 1, wherein each of the plurality of phase-mode D flip-flops is transformer-coupled to an AC bias signal source or a DC bias signal source weaker or stronger than the JTL of the operating RQL circuit on the RQL IC that is not part of the phase-mode shift register.
7. The RQL IC according to claim 6, wherein the individual transformer coupling of each of the plurality of phase-mode D flip-flops is set in steps such that the strength of the individual transformer coupling of each phase-mode D flip- flop changes relative to one another.
8. The RQL IC according to claim 6, wherein the lower limit of the AC operating range of at least one of the plurality of phase-mode D flip-flops is approximately at the centroid of the operating range of the operating RQL circuit.
9. The RQL IC according to claim 1, wherein each of the second plurality of JTLs in the logic clock path trunk is biased by an AC bias signal source less strongly than the JTLs of the operating RQL circuit on the RQL IC that are not part of the phase mode shift register .
10. The RQL IC according to claim 9, wherein the lower limit of the AC operating range of each of the second plurality of JTLs in the logic clock path trunk is approximately at the centroid of the operating range of the operating RQL circuit.

Description

This disclosure relates, in general terms, to superconducting circuits, and more specifically, to phase-mode bit-addressable sensing registers. In the field of digital logic, well-known and highly developed complementary metal-oxide-semiconductor (CMOS) technology is widely used. As CMOS technology has matured, interest is growing in alternative technologies that can offer higher performance in terms of speed, power consumption, computational density, and interconnect bandwidth. As an alternative to CMOS technology, single-flux quantum (SFQ) circuits utilize superconducting Josephson junctions (JJ) with typical signal power of approximately 4 nanowatts (nW), typical data rates of 20 gigabits per second (Gb/s) or more, and operating temperatures of approximately 4 Kelvin. The family of SFQ circuits, known as reciprocal quantum logic (RQL), uses one or more resonator networks and/or bias lines to distribute one or more bias signals. The bias signals serve to bias the JJs within the logic gates of the RQL circuit and the Josephson transmission lines (JTLs), which are found within the gates of the RQL circuit or as inter-gate connecting lines for propagating SFQ signals within the RQL circuit. The AC bias signals can function as one or more global clock signals that can help eliminate clock jitter, as may be exhibited by earlier superconducting circuit technologies such as rapid single-flux quantum (RSFQ) logic. For example, RQL can utilize a multiphase clock having an in-phase (I) clock signal and an orthogonal (Q) clock signal that is approximately 90° out of phase with the I clock signal. An exemplary RQL integrated circuit (IC) includes a phase-mode shift register having a first plurality of JTLs arranged in series as a data path, a second plurality of JTLs arranged in series as a logic clock path trunk, and a plurality of phase-mode D flip-flops. Each phase-mode D flip-flop has (1) a data input coupled to the data path and configured to receive input from the data path, (2) a data output coupled to the data path and configured to provide output to the data path, and (3) a logic clock input coupled to a branch of an individual logic clock path coupled to the logic clock path trunk. The first plurality of JTLs in the data path and the phase-mode D flip-flops are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of two first AC clock phases separated by approximately 180° from each other. The second set of JTLs within the logic clock path trunk are transformer-coupled to one or more AC clock resonators of the RQL IC to receive AC clock bias signals of two second AC clock phases separated by approximately 180° in phase from each other. The first two AC clock phases are different from the second two AC clock phases. An exemplary method includes the steps of setting at least one bias signal parameter of the bias signal supplied to the RQL IC to a nominal value, and starting a logic clock signal supplied to the logic clock path of the phase-mode RQL shift register to shift in the input data bit pattern to the data path of the phase-mode RQL shift register. The logic clock is then stopped, and the value of at least one bias signal parameter supplied to the data path of the phase-mode RQL shift register is changed to a value different from the nominal value. A pair of assertion SFQ pulses, or a single SFQ pulse, is input to the logic clock path. When the value of at least one bias signal parameter is returned to the nominal value, the logic clock signal supplied to the logic clock path of the phase-mode RQL shift register is restarted, and the output data bit pattern is shifted out to the data path of the phase-mode RQL shift register. The output data bit pattern of the phase-mode RQL shift register is observed. Based on observation of the output data bit pattern, it is determined that the value of at least one bias signal parameter approaches (or has approached) its optimal value by changing the value of at least one bias signal parameter. The bias signal parameter being changed may be the AC bias amplitude, DC bias value, or AC bias signal phase. Another exemplary RQL superconducting bias level sensing circuit for sensing the bias level supplied to the RQL circuit of an RQL IC comprises a phase-mode logic (PML) shift register including a plurality of PML shift register elements coupled in series with each other. Each PML shift register element includes a PML D flip-flop having a data input, a data output, and a logic clock input, wherein the data input is configured to be coupled to either the data output of the previous element in the PML shift register or an input data bitstream source. Each PML shift register element further includes a data output path portion having an input coupled to the data output of the PML D flip-flop and an output configured to be coupled to either the data input of the next element in the PML shift register or a circuit configured to