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JP-7855824-B2 - Method for manufacturing a multilayer ceramic capacitor and multilayer ceramic capacitor

JP7855824B2JP 7855824 B2JP7855824 B2JP 7855824B2JP-7855824-B2

Inventors

  • オー、ヨン ジョーン
  • パク、セオン ハン
  • キム、ジェオン リョル

Assignees

  • サムソン エレクトロ－メカニックス カンパニーリミテッド．

Dates

Publication Date
20260511
Application Date
20220426
Priority Date
20211215

Claims (8)

  1. The steps include providing a ceramic green sheet on which multiple internal electrode patterns are formed at predetermined intervals, The steps include: stacking a large number of the aforementioned ceramic green sheets in a first direction to form a ceramic laminate; The steps include cutting the ceramic laminate such that the end of the internal electrode pattern has a side surface exposed in a second direction perpendicular to the first direction, The steps include forming a margin portion on the side surface where the end of the internal electrode pattern is exposed, The process includes the step of firing the cut ceramic laminate to form a ceramic body including a dielectric layer and internal electrodes, A method for manufacturing a multilayer ceramic capacitor, wherein the step of forming the margin portion includes the step of pouring ceramic paste from the top to the bottom of the cut ceramic laminate.
  2. The method for manufacturing a multilayer ceramic capacitor according to claim 1, wherein the ceramic paste has a higher viscosity than the ceramic slurry used to form the ceramic green sheet.
  3. The method for manufacturing a multilayer ceramic capacitor according to claim 1, wherein the step of forming the margin portion further includes the step of drawing the ceramic paste from the lower part of the cut ceramic laminate.
  4. The method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the margin portion has a higher density than the dielectric layer.
  5. The step of forming the margin portion is performed in a state where the ceramic laminate is cut and formed into multiple laminated bars, according to any one of claims 1 to 3, for the method of manufacturing a multilayer ceramic capacitor.
  6. The step of forming the margin portion is performed in a plurality of stacked chip states formed by cutting the ceramic stack, according to the method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 3.
  7. The method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the average thickness of the margin portion is 2 μm to 15 μm.
  8. A method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the average thickness of the dielectric layer is 0.4 μm or less.

Description

This invention relates to a method for manufacturing a multilayer ceramic capacitor and to a multilayer ceramic capacitor. Generally, electronic components using ceramic materials, such as capacitors, inductors, piezoelectric elements, varistors, or thermistors, comprise a ceramic body made of ceramic material, internal electrodes formed inside the body, and external electrodes provided on the surface of the ceramic body to connect to the internal electrodes. Recently, as electronic products have become smaller and more multifunctional, chip components have also tended to become smaller and more sophisticated. Therefore, there is a demand for multilayer ceramic capacitors that are small in size and have high capacitance. Conventionally, margins were formed by firing the remaining region of the ceramic green sheet, excluding the area where the internal electrode pattern was formed. However, this process of laminating, compressing, and cutting tens to hundreds of layers of ceramic green sheet resulted in unevenness and warping of the internal electrode pattern. This led to a decrease in the reliability of multilayer ceramic capacitors. To solve this problem, conventional methods have involved maximizing the widthwise surface area of the internal electrodes by exposing them in the width direction of the chip, thereby eliminating margins. After fabricating such chips, a margin portion is separately attached to the exposed electrode surface in the width direction of the chip before firing. However, conventionally, when manufacturing multilayer ceramic capacitors as described above, the dielectric composition for forming the margin portion was not differentiated from the dielectric composition of the ceramic body; the dielectric composition of the ceramic body was used as is. This resulted in a decrease in the physical packing density of the dielectric material within the margin, leading to a problem of reduced density in the margin. Furthermore, a problem arose where the interfacial gap between the edges of the internal electrodes and the junction surface of the margin was not filled due to sintering mismatching between the dielectric material in the margin and the internal electrodes during the sintering process. This, in turn, led to a decrease in the moisture resistance reliability of the multilayer ceramic capacitor. Furthermore, the conventional technology described above involves physically pressing a ceramic green sheet, which acts as a margin, onto a green chip cut without a margin, and then constructing a sintered body with a rigid main body through high-temperature heat treatment. However, if the adhesive strength between the margin-forming sheet and the electrode exposed surface is insufficient in the pre-sintering stage, it can lead to serious defects such as detachment of the margin, resulting in poor appearance and interface cracks. Furthermore, during high-temperature heat treatment, the shrinkage of the internal electrodes causes a volume change inside the chip. This can create voids at the interface between the electrode ends and the margin, potentially acting as a starting point for crack formation or becoming a moisture penetration pathway, leading to a decrease in moisture resistance reliability. Japanese Patent Publication No. 2019-016688 This is a schematic perspective view of a multilayer ceramic capacitor according to one embodiment of the present invention.This is a schematic perspective view of the ceramic body of a multilayer ceramic capacitor.This is a schematic cross-sectional view showing a section along the line I-I' in Figure 1.This is a schematic cross-sectional view showing a section along the line II-II' in Figure 1.These are schematic cross-sectional and perspective views illustrating a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention.These are schematic cross-sectional and perspective views illustrating a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention.These are schematic cross-sectional and perspective views illustrating a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention.These are schematic cross-sectional and perspective views illustrating a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention.These are schematic cross-sectional and perspective views illustrating a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention.This is a schematic perspective view of the laminated body according to one embodiment of the present invention.This is a schematic perspective view of the laminated body according to one embodiment of the present invention.This graph shows the results of the humidity resistance reliability test using a comparative example.This graph shows the results of a humidity resistan