JP-7855826-B2 - Manufacturing method for railway devices

JP7855826B2JP 7855826 B2JP7855826 B2JP 7855826B2JP-7855826-B2

Inventors

林茂雄
周健康
陳科宏

Assignees

クゥアルコム・インコーポレイテッド

Dates

Publication Date: 20260511
Application Date: 20230215
Priority Date: 20050624

Claims (8)

A circuit structure, Semiconductor substrate and A number of transistors on the aforementioned semiconductor substrate, A connection structure bonded to the semiconductor substrate, wherein the connection structure comprises a plurality of dielectric layers and a plurality of line layers . An insulating layer bonded to the uppermost of the plurality of dielectric layers comprising the connection structure, wherein the insulating layer comprises a nitride layer, and wherein a first opening in the insulating layer exposes the contact point of the connection structure. A first conductive layer bonded to the insulating layer on the contact point, wherein the first conductive layer is bonded to the contact point through the first opening, and wherein the first conductive layer has a thickness between 2 micrometers and 30 micrometers, is bonded to the contact point, and is bonded to the insulating layer. A first conductive column on the first conductive layer, wherein the first conductive column is in contact with the first conductive layer, and wherein the first conductive column is coupled to the contact point through the first conductive layer. A first polymer material on the first conductive layer, wherein the first polymer material is in contact with the side wall of the first conductive column, and wherein the first polymer material has a first surface at the same level as the second surface of the first conductive column. A second polymer material on the first polymer material, wherein the opening in the second polymer material exposes the second surface of the first conductive column. A second conductive layer bonded to the second surface of the first conductive column, on the surface of the second polymer material around the opening, and on the inner wall of the opening that exposes the second surface of the first conductive column, wherein the second conductive layer has a thickness between 400 Å and 7000 Å. The tin-containing solder on the second conductive layer, wherein the tin-containing solder is connected to the second conductive layer and connected to the first conductive layer through the first conductive column, and at least a portion of the tin-containing solder is in the opening that exposes the second surface of the first conductive column. The insulating layer further comprises a polymer layer, wherein a second opening in the polymer layer exposes the contact point, and the first conductive layer further comprises the polymer layer and the second opening. A circuit structure that includes the following features.
The circuit structure according to claim 1, further comprising a second conductive column bonded to the semiconductor substrate and located in the first polymerized material, wherein the second conductive column has a third surface at the same horizontal level as the first and second surfaces, and the distance between the first conductive column and the second conductive column is between 10 micrometers and 250 micrometers.
The circuit structure according to claim 1, wherein the second circuit layer comprises electroplated copper.
The circuit structure according to claim 1, wherein the nitride layer has a thickness between 0.2 micrometers and 1.2 micrometers.
The circuit structure according to claim 1, wherein the first conductive layer is bonded to the insulating layer and further comprises a titanium-containing layer on the contact point, wherein the first conductive layer is further bonded to the titanium-containing layer.
The circuit structure according to claim 1, further comprising a copper layer and a nickel layer on the second surface, wherein the tin-containing solder is further bonded to the nickel layer.
The circuit structure according to claim 6 , wherein the nickel layer has a thickness between 1 micrometer and 10 micrometers.
The circuit structure according to claim 1, wherein the tin-containing solder comprises a tin-silver alloy.

Description

This invention relates to a method for manufacturing a transmission line device, and more particularly to a method for manufacturing a transmission line device that effectively improves the performance of an IC. Semiconductor wafers are used in the manufacture of ICs, where density is continuously increasing and geometric patterns are reduced. Through the multilayer structure of conductive and insulating layers, they provide internal connectivity and isolation between semiconductor devices in different layers. For example, in large ICs such as active and passive devices, thin-film transistors, CMOS (Crystal Monetary Sensors), capacitors, chokers, and resistors, several additional electromagnetic connection points are required between different layered structures and semiconductor devices. Simultaneously, a significant increase in wires is also necessary for assembled ICs. These wires pass through the protective layer within the IC chip, are exposed to the outside, and finally connect to output and input pads. These wires are used to connect to the external contact structure of the chip packaging. Wafer-level chip-scale packaging (WLCSP) is a technology for packaging IC chips at the wafer level, differing from the traditional process of cutting chips and then manufacturing single-unit packages. Therefore, before cutting chips into single units and before final chip carrier packaging, such as ball grid array (BGA) packaging, WLCSP allows for the integration of wafer manufacturing, packaging, testing, and wafer-level burn-in (WLBI). Its advantages include reduced volume and thickness, resulting in smaller dimensions, lighter weight, a relatively simpler assembly process, lower overall production costs, and better electromagnetic properties. Furthermore, WLCSP simplifies the transportation process from silicon material to customer site, increasing IC chip package production while simultaneously reducing costs. However, it faces significant challenges due to its reliance on manufacturing capability and structural reliability. WLCSP can be extended to the bonding device fabrication process and device protection fabrication process during the wafer fabrication process. In the first step of WLCSP, post-passivation is formed through reconfigurable semiconductor IC line technology, widening the distance between standard pads. This allows for the formation of low-cost solder stencils, and sil or aligned soldering is realized. Regarding the publication of reconfigurable technology, for example, the applicants of Patent Documents 1-3 are the same as the applicants of this invention, and as published in this patent, a single line arrangement layer is connected to the output input pads of the semiconductor structure. This RDL layer is formed on the post-passivation polymer layer or elastic material layer, and a post-shaped contact window manufactured using the mask fabrication process is formed on this RDL layer. The lateral direction of the post-shaped contact window formed after this reaction is independent and not supported at all, and furthermore, using flip-chip assembly technology, the structure formed after the above reaction is taken a step further and assembled into a chip carrier package. While this post-passivation structure and its corresponding manufacturing process can solve and improve the problem of spacing within IC packages, ICs requiring sustained increases in integrated scale should be subject to more stringent limitations, and there is also a potential risk of damage caused by stress induction. Patent Document 4 includes a WLCSP with a post-passivation structure for another RDL layer. This RDL layer is formed on a polymer layer above the post-passivation, and another polymer layer is placed over the RDL layer. Micro-vias are formed in this polymer layer by etching or drilling, and metal is used to fill the holes in the micro-vias to form internal connections, creating a so-called conductive column. However, the upper and lower polymer layers are separated by a chromium-copper layer to prevent contact with the RDL layer, and the other is bonded to a non-electroplated, screen-printed, or stenciled tin-lead at the protruding tail end of the conductive column. Since the conductive column extends outside the polymer layer, and the top surface of the above structure is not smooth, high-resolution lithography cannot be achieved. As a result, the formation of micro-vias in the conductive column and the formation of tin-lead by electroplating cannot be achieved, and ultimately the spacing distance of the contact windows in the IC package is limited. Furthermore, this limitation becomes increasingly noticeable as the thickness of the polymer layer increases. However, increasing the thickness of the polymer layer provides satisfactory stress relief. This point will be discussed below. Furthermore, as mentioned above, because the lower polymer layer is isolated from the upper polymer layer, the lower polymer laye