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JP-7855832-B2 - Multilayer capacitor and its mounting substrate

JP7855832B2JP 7855832 B2JP7855832 B2JP 7855832B2JP-7855832-B2

Inventors

  • キム、フイ ダエ
  • ジョ、ジ ホン
  • シン、ウー チュル
  • ユーン、チャン
  • パク、サン スー

Assignees

  • サムソン エレクトロ－メカニックス カンパニーリミテッド．

Dates

Publication Date
20260511
Application Date
20200622
Priority Date
20190717

Claims (7)

  1. A capacitor body including a dielectric layer and a plurality of first and second internal electrodes, The capacitor body includes first and second external electrodes, which are respectively positioned at both ends and connected to the exposed portions of the first and second internal electrodes, When the thickness of the dielectric layer is defined as A and the average length of the margin in the longitudinal direction of the capacitor body is defined as B, then A is 1 μm or less and A/B satisfies 0.04 ≤ A/B < 1. A multilayer capacitor in which the thickness of the first and second internal electrodes is 0.4 μm or less.
  2. The capacitor body includes first and second surfaces facing each other, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces, The multilayer capacitor according to claim 1 , wherein the first and second internal electrodes are arranged such that one end of each electrode is alternately exposed on the third and fourth surfaces of the capacitor body, with a dielectric layer in between.
  3. The first and second external electrodes are, First and second connection portions are formed on the third and fourth surfaces of the capacitor body, respectively, and are connected to the exposed portion of the internal electrode. A multilayer capacitor according to claim 1 or 2 , comprising, respectively, first and second band portions extending from the first and second connection portions to a part of the first surface of the capacitor body.
  4. The plating layer further includes a layer formed to cover the first and second external electrodes, The multilayer capacitor according to any one of claims 1 to 3 , wherein the plating layer comprises a nickel plating layer and a tin plating layer.
  5. The multilayer capacitor according to any one of claims 1 to 4 , wherein the thickness of the dielectric layer is 1 μm and A/B satisfies 0.04 ≤ A/B ≤ 0.2.
  6. The multilayer capacitor according to any one of claims 1 to 4 , wherein the thickness of the dielectric layer is 0.4 μm and A/B satisfies 0.04 ≤ A/B ≤ 0.5.
  7. A substrate having first and second electrode pads on one surface, A mounting substrate for a multilayer capacitor, comprising a multilayer capacitor according to any one of claims 1 to 6 , wherein the first and second external electrodes are mounted on the first and second electrode pads, respectively.

Description

This invention relates to a multilayer capacitor and its mounting substrate. A multilayer capacitor (MLCC) is a passive component that plays a role in controlling electrical signals in a circuit. The main role of a multilayer capacitor is to store electric charge within its electrodes, acting as a filter that blocks direct current (DC) signals and allows alternating current (AC) signals to pass through. In other words, multilayer capacitors play a role in stabilizing IC operation by bypassing and removing AC noise from the power line. Various methods have been attempted to increase the capacitance of such MLCCs. For example, methods such as increasing the dielectric constant of the dielectric, reducing the thickness of the dielectric layer, or increasing the overlapping area of the internal electrodes have been disclosed. However, increasing the overlapping area of the internal electrodes reduces the margin in the length or width direction of the product. If the reduction in margin is too large, it can lead to a problem where the electric field characteristics weaken. Korean Registered Patent Publication No. 10-1761936 This is a schematic perspective view of a multilayer capacitor according to one embodiment of the present invention.(a) and (b) are plan views showing the first and second internal electrodes applied to the multilayer capacitor in Figure 1, respectively.This is a cross-sectional view along the line I-I' in Figure 1.Figure 3 is a cross-sectional view showing that an additional plating layer has been formed on the external electrode.This is a cross-sectional view of the capacitor body, illustrating the position where the electric field is measured during an electric field measurement test.Figure 4 is a schematic cross-sectional view showing the multilayer capacitor mounted on a substrate. The following describes preferred embodiments of the present invention with reference to the accompanying drawings. However, embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to provide a more complete explanation of the present invention to those with average skill in the art. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements. Furthermore, throughout the specification, the phrase "includes" a certain component means, unless otherwise specifically contradicted, that other components may be included, rather than being excluded. To clearly explain the embodiments of the present invention, the orientation of the capacitor body 110 is defined as follows: X, Y, and Z shown in the drawings represent the length, width, and thickness directions of the capacitor body 110, respectively. Furthermore, in this embodiment, the Z direction can be used with the same concept as the stacking direction in which the dielectric layers are stacked. Figure 1 is a schematic perspective view of a multilayer capacitor according to one embodiment of the present invention; Figures 2(a) and 2(b) are plan views showing the first and second internal electrodes applied to the multilayer capacitor of Figure 1, respectively; and Figure 3 is a cross-sectional view along the line I-I' in Figure 1. Referring to Figures 1 to 3, the multilayer capacitor 100 according to this embodiment includes a capacitor body 110 comprising a dielectric layer 111 and a plurality of first and second internal electrodes 121 and 122, and first and second external electrodes 131 and 141, respectively, which are arranged at both ends of the capacitor body 110 and connected to the exposed portions of the first and second internal electrodes 121 and 122. In this case, when the thickness of the dielectric layer 111 is defined as A and the length of the margin in the X direction of the capacitor body 110 is defined as B, A is 1 μm or less, and the ratio of the thickness of the dielectric layer to the length of the margin in the X direction of the capacitor body, A/B, can satisfy 0.0016 ≤ A/B < 1. The capacitor body 110 is formed by stacking multiple dielectric layers 111 in the Z direction and then firing them. The boundaries between adjacent dielectric layers 111 of the capacitor body 110 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM). In this case, the capacitor body 110 may be generally hexahedral, but the present invention is not limited to this. Furthermore, the shape, dimensions, and number of layers of the dielectric layer 111 of the capacitor body 110 are not limited to those shown in the drawings of this embodiment. In this embodiment, for the sake of explanation, the two surfaces of the capacitor body 110 facing each other in th