Search

JP-7855836-B2 - Semiconductor equipment

JP7855836B2JP 7855836 B2JP7855836 B2JP 7855836B2JP-7855836-B2

Inventors

  • 中村 賢平

Assignees

  • 富士電機株式会社

Dates

Publication Date
20260511
Application Date
20210615

Claims (13)

  1. A lead frame having an upper surface with a recess and a lower surface with a protrusion, A semiconductor chip fixed to the upper surface of the lead frame, A solder layer provided in the recess, in contact with the bottom surface of the recess, and fixing the semiconductor chip to the upper surface of the lead frame, The semiconductor chip and the lead frame are enclosed by a sealing resin, The thickness of the solder layer is greater than the depth of the recess. The sealing resin covers at least a portion of the lower surface of the lead frame, At least a portion of the protrusion of the lead frame is exposed from the sealing resin. In a top view, the entire semiconductor chip is positioned overlapping the recess. A semiconductor device wherein the depth of the recess directly below the edge of the semiconductor chip in a top view is greater than the depth of the recess directly below the center of the semiconductor chip in a top view.
  2. The semiconductor device according to claim 1, wherein the depth of the recess directly below the corner of the semiconductor chip in a top view is greater than the depth of the recess directly below the center of the semiconductor chip in a top view.
  3. The semiconductor device according to claim 1 or 2, wherein the corner of the recess has a curve when viewed from above.
  4. The semiconductor device according to claim 1, wherein the edge of the convex portion, when viewed from above, has an uneven surface.
  5. The semiconductor device according to claim 4, wherein the end edge of the convex portion protrudes toward the semiconductor chip at a position opposite to the corner of the semiconductor chip.
  6. The semiconductor chip is further equipped with an external terminal that is electrically connected to the aforementioned semiconductor chip. The semiconductor device according to claim 4 or 5, wherein the end edge of the protrusion protrudes toward the semiconductor chip at a position opposite to the external terminal.
  7. The semiconductor chip is further provided with an external terminal for connection, The semiconductor device according to any one of claims 1 to 6, wherein the external terminal has a protruding portion that protrudes when viewed from above.
  8. The semiconductor device according to claim 7, wherein the external terminal is provided at a position lower than the semiconductor chip in the height direction.
  9. The semiconductor device according to any one of claims 1 to 8, wherein the height of the protrusion is less than or equal to the depth of the recess.
  10. A lead frame having an upper surface with a recess and a lower surface with a protrusion, A semiconductor chip fixed to the upper surface of the lead frame, A solder layer provided in the recess, in contact with the bottom surface of the recess, and fixing the semiconductor chip to the upper surface of the lead frame, The semiconductor chip and the lead frame are enclosed by a sealing resin, The thickness of the solder layer is greater than the depth of the recess. The sealing resin covers at least a portion of the lower surface of the lead frame, At least a portion of the protrusion of the lead frame is exposed from the sealing resin. In a top view, the entire semiconductor chip is positioned overlapping the recess. The sealing resin has a filler, A semiconductor device in which the filler is provided in a region below the lead frame where the protrusion is not provided.
  11. The semiconductor device according to any one of claims 1 to 10, wherein the solder layer is in contact with the side surface of the recess.
  12. The semiconductor device according to any one of claims 1 to 11, wherein the solder layer is provided over the entire bottom surface of the recess.
  13. A lead frame having an upper surface with a recess and a lower surface with a protrusion, A semiconductor chip fixed to the upper surface of the lead frame, A solder layer provided in the recess, in contact with the bottom surface of the recess, and fixing the semiconductor chip to the upper surface of the lead frame, The semiconductor chip and the lead frame are enclosed by a sealing resin, The thickness of the solder layer is greater than the depth of the recess. The sealing resin covers at least a portion of the lower surface of the lead frame, At least a portion of the protrusion of the lead frame is exposed from the sealing resin. In a top view, the entire semiconductor chip is positioned overlapping the recess. A semiconductor device in which, when viewed from above, the entire region where the protrusion is provided overlaps with the region where the recess is provided.

Description

This invention relates to a semiconductor device. Conventionally, semiconductor devices have been known in which a semiconductor chip is fixed to a die pad or the like on a lead frame using a fixing part such as solder (see, for example, Patent Documents 1-3). The following are related prior art documents (see Patent Documents 4-6). Patent Document 1: Japanese Unexamined Patent Publication No. 2018-174232 Patent Document 2: Japanese Unexamined Patent Publication No. 2015-43380 Patent Document 3: Japanese Unexamined Patent Publication No. 2017-135230 Patent Document 4: Japanese Unexamined Patent Publication No. 2008-34601 Patent Document 5: Japanese Unexamined Patent Publication No. 2014-232811 Patent Document 6: Japanese Unexamined Patent Publication No. Hei 11-145363 This is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention.This figure shows an example of a semiconductor device 100 in cross-section a-a.This is a bottom view showing an example of a semiconductor device 100.This is a side view showing an example of an external terminal 22.This is a top view showing an example of a semiconductor device 200 according to another embodiment of the present invention.This figure shows an example of a semiconductor device 200 in a b-b cross-section.This is a top view showing an example of a semiconductor device 300 according to another embodiment of the present invention.This is a top view showing an example of a semiconductor device 400 according to another embodiment of the present invention.This is a bottom view showing an example of a semiconductor device 400.This is a top view showing an example of a semiconductor device 500 according to another embodiment of the present invention.This is a bottom view showing an example of a semiconductor device 500.This is a top view showing an example of a semiconductor device 600 according to another embodiment of the present invention.This is a bottom view showing an example of a semiconductor device 600.This is a diagram illustrating the sealing resin 10 in detail. The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification, one side of a semiconductor chip parallel to its thickness is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, lead frame, or other component, one surface is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted. This specification may use the X, Y, and Z axes of a Cartesian coordinate system to describe technical matters. The Cartesian coordinate systems merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When "Z axis direction" is written without specifying positive or negative, it means the direction parallel to the +Z and -Z axes. In this specification, the thickness direction of the semiconductor chip is defined as the Z axis direction, and the plane parallel to the top surface of the semiconductor chip is defined as the XY plane. Note that the X and Y axis directions are parallel to either edge of the top surface of the semiconductor chip. Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 comprises a semiconductor chip 80. The semiconductor chip 80 is a chip on a semiconductor substrate such as silicon, on which semiconductor elements such as transistors and diodes are formed. The semiconductor elements may be insulated-gate bipolar transistors (IGBTs) or power semiconductor elements such as power MOSFETs. Figure 1 shows an example of the arrangement of each component in the XY plane parallel to the top surface 79 of the semiconductor chip 80. Although the semiconductor device 100 in this example comprises one semiconductor chip 80, the number of semiconductor chips 80 in the semiconductor device 100 may be two or more. As an example, the semiconductor device 100 is an intelligent power switch. The semiconductor device 100 includes a lead frame on which a semiconductor chip 80 is fixed. In this example, the semiconductor device 100 includes a lead frame 12 on which one semiconductor chip 80 is fixed. The lead frame 12 is made of aluminum, copper, or other metallic material. The lead frame 12 may have a plate shape. A plate shape refers to a shape where the area of each of the two opposing main surfaces (upper surface 11 and lower surfa