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JP-7855910-B2 - Semiconductor unit

JP7855910B2JP 7855910 B2JP7855910 B2JP 7855910B2JP-7855910-B2

Inventors

  • 五十嵐 征輝

Assignees

  • 富士電機株式会社

Dates

Publication Date
20260511
Application Date
20220422

Claims (9)

  1. One or more capacitors having a first terminal and a second terminal, Multiple semiconductor modules, each having a positive terminal, a negative terminal, and a first output terminal, A laminate wiring comprising a first conductor connecting the first terminal to each of the positive terminals, a second conductor connecting the second terminal to each of the negative terminals, and an insulator disposed between the first conductor and the second conductor to insulate the first conductor and the second conductor, wherein a slit is provided in at least one of the first conductor and the second conductor, so that the variation in the sum of the inductance values from the first terminal to the nearest positive terminal and the inductance values from the negative terminal to the nearest second terminal is 10 nH or less among the plurality of semiconductor modules, Output wiring having each connection part connected to each of the first output terminals, a second output terminal, and an intermediate part that electrically connects each of the connection parts and the second output terminal, A semiconductor unit equipped with the following features.
  2. The semiconductor unit according to claim 1, wherein the slits are provided in both the first conductor and the second conductor and are positioned to overlap in a plan view.
  3. The semiconductor unit according to claim 1, wherein the slit is provided such that at least one of the wiring widths of the path of the first conductor connecting the first terminal and the positive terminal, or the wiring width of the path of the second conductor connecting the second terminal and the negative terminal, becomes narrower as the distance to the one or more capacitors decreases.
  4. The semiconductor unit according to any one of claims 1 to 3, wherein the output wiring has an inductance variation of 10 nH or less from each connection point to the second output terminal.
  5. The semiconductor unit according to claim 1, wherein the intermediate portion is formed such that the wiring width increases as it moves away from the second output terminal.
  6. The semiconductor unit according to claim 1, wherein the plurality of semiconductor modules are arranged in a ring, the positive terminal of each of the plurality of semiconductor modules is electrically connected to the first terminal via the first conductor located in the central part of the ring, and the negative terminal of each of the plurality of semiconductor modules is electrically connected to the second terminal via the second conductor located in the central part.
  7. The semiconductor unit according to claim 6, wherein the plurality of semiconductor modules arranged in a ring are positioned such that the longest of the three sides representing height, length, or width is parallel to the central axis of the ring.
  8. The semiconductor unit according to claim 6, wherein each connection portion of the output wiring is formed to extend in the direction of the central axis of the ring from the first output terminal of each of the plurality of semiconductor modules arranged in a ring.
  9. The semiconductor unit according to claim 6, wherein each of the output wiring and the laminate wiring includes a coaxial wiring section with the central axis of the ring being coaxial.

Description

This invention relates to a semiconductor unit having multiple parallel-gear semiconductor modules. To improve current carrying capacity, there are semiconductor units that connect multiple semiconductor modules in parallel, each containing switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Furthermore, there is a technique for connecting multiple semiconductor modules in parallel using laminate wiring containing a first conductor and a second conductor. For example, the positive terminal of each semiconductor module is connected to the first conductor, which is connected to one of the two terminals of a capacitor functioning as a DC power supply, and the negative terminal of each semiconductor module is connected to the second conductor, which is connected to the other terminal of the capacitor. The output terminals of the multiple semiconductor modules are electrically connected to the output terminals of a semiconductor unit. Conventionally, in inverter units containing multiple semiconductor switches connected in parallel, there is a technique that arranges the output wiring opposite the input wiring, aligning the current paths to the longest possible path to prevent current imbalance (see, for example, Patent Document 1). However, in this structure, the current path becomes longer, increasing the wiring inductance and thus the surge voltage during switching. Furthermore, the path through which high-frequency current flows during switching also becomes longer, leading to EMI (Electro-Magnetic Interference) problems such as radiated noise. Furthermore, it has been proposed to provide slits in busbars to resolve current imbalances in semiconductor modules connected in parallel (see, for example, Patent Documents 2 and 3). Also, in multiple semiconductor chips connected in parallel, it is known that the emitter electrodes of each chip are connected to the same conductive material via individually positioned terminals (see, for example, Patent Document 4). Furthermore, regarding the arrangement of multiple semiconductor modules, there is a method in which a capacitor module is provided around a rotating axis, and multiple semiconductor modules are arranged circumferentially on the outer surface of the capacitor module (see, for example, Patent Document 5). Another method involves arranging multiple semiconductor modules concentrically around a cylindrical case with a hole formed for passing a motor shaft or the like (see, for example, Patent Document 6). Furthermore, there is a technique that detects the circulating current flowing through the wiring connected to the emitters of parallel-connected switching elements and controls the on/off state of each switching element using a gate drive circuit based on the result (see, for example, Patent Document 7). Japanese Patent Publication No. 2016-174503Japanese Patent Publication No. 2017-139915Japanese Patent Publication No. 2006-203974Japanese Patent Publication No. 2020-156310Japanese Patent Publication No. 2021-19383International Publication No. 2016-125673Japanese Patent Publication No. 2015-149828 This is a plan view showing a semiconductor unit according to the first embodiment.This is a perspective view showing an example of slits provided in the first and second conductors.This figure shows an example of an equivalent circuit of the semiconductor unit according to the first embodiment.This is a plan view showing a semiconductor unit of a comparative example.This figure shows the equivalent circuit of a comparative semiconductor unit.This is a plan view showing a modified example of the semiconductor unit according to the first embodiment.This is a plan view showing a semiconductor unit according to a second embodiment.This is a cross-sectional view along the line VIII-VIII in Figure 7.This is a plan view showing the connection relationship between the capacitor and the laminated wiring.This is a perspective view showing an example of a coaxial wiring section.This is a plan view showing a modified example of the semiconductor unit according to the second embodiment.This is a cross-sectional view along the line XII-XII in Figure 11. The embodiments for carrying out the invention will be described below with reference to the drawings. In the following description, "top," "bottom," "front surface," and "back surface" are merely convenient terms to specify relative positional relationships and do not limit the technical concept of the present invention. For example, "top" and "bottom" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "top" and "bottom" are not limited to the direction of gravity. (First Embodiment) Figure 1 is a plan view showing a semiconductor unit according to the first embodiment. The semiconductor unit 10 has one or more capacitors (four capacitors 11a, 11b, 11c, and 11d in the example of Figu