JP-7856144-B2 - Multilayer ceramic capacitor

JP7856144B2JP 7856144 B2JP7856144 B2JP 7856144B2JP-7856144-B2

Inventors

木村健二
浦谷幸祐
笹林武久

Assignees

株式会社村田製作所

Dates

Publication Date: 20260511
Application Date: 20230426
Priority Date: 20220512

Claims (3)

A laminate comprising: an inner layer portion formed by alternately stacking multiple dielectric layers and internal electrode layers; a pair of outer layer portions sandwiching the inner layer portion from the stacking direction; and a pair of side margin portions sandwiching the inner layer portion and the outer layer portion from a width direction perpendicular to the stacking direction; A pair of external electrodes, consisting of a first external electrode and a second external electrode, are arranged at both ends of the laminate in the length direction perpendicular to the lamination direction and the width direction, and are electrically connected to the first internal electrode layer and the second internal electrode layer that constitute the internal electrode layer, respectively. A multilayer ceramic capacitor equipped with, When the laminate is cut at the central position in the longitudinal direction and the cross-section defined in the width direction and the lamination direction is viewed, In the side margin portion, a crystalline oxide containing at least one of Al, Mg, and Si exists as an elongated secondary phase with an aspect ratio of 12.4 to 20. A multilayer ceramic capacitor in which 90 atomic percent or more of the Mg contained in the crystalline oxide is made of a composite oxide containing Al, Mg, and Si .
The multilayer ceramic capacitor according to claim 1 , wherein the thickness of the dielectric layer sandwiched between the internal electrode layers in the stacking direction is 0.45 μm or less.
The multilayer ceramic capacitor according to claim 1 or claim 2 , wherein the external dimensions of the laminate are 1.0 mm or less in length, 0.5 mm or less in width, and 0.5 mm or less in height.

Description

This invention relates to a multilayer ceramic capacitor. A multilayer ceramic capacitor generally comprises a laminate in which dielectric layers and internal electrode layers are alternately stacked, with dielectric layers further stacked on the upper and lower surfaces, and a pair of external electrodes formed on both end faces of the laminate. However, in order to relatively increase the area of the internal electrode layer, some multilayer ceramic capacitors have a structure in which the laminate comprises an inner layer portion having capacitance by stacking dielectric layers and internal electrode layers, and a side margin portion with dielectric layers arranged on both sides of the inner layer portion (for example, Patent Document 1). In such multilayer ceramic capacitors, in order to further reduce the size and increase the capacitance in response to the miniaturization and multi-functionality of electronic products in recent years, it is important to reduce the thickness in the width direction of the side margin portion and enlarge the inner layer portion to secure a larger area for the internal electrode layer. However, when a laminated structure with side margins is fired, differences in shrinkage rates easily create gaps between the inner layer and the side margins, particularly between the edges of the internal electrode layer and the left and right side margins. Moisture then penetrates these gaps, degrading the insulation resistance between the dielectric layers and reducing the functionality of the multilayer ceramic capacitor. This problem becomes more severe as the widthwise thickness of the side margins decreases, compromising the reliability of the multilayer ceramic capacitor. Therefore, there is a need to develop multilayer ceramic capacitors that are small, have high capacity, and possess high reliability. Japanese Patent Application Publication No. 10-50545 This is a schematic perspective view showing an example of the multilayer ceramic capacitor of the present invention.Figure 1 is a schematic perspective view showing an example of a laminate that makes up a multilayer ceramic capacitor.Figure 1 is a cross-sectional view of the multilayer ceramic capacitor shown along line A-A.Figure 1 is a cross-sectional view of a multilayer ceramic capacitor along the C-C line.Figure 1 is a cross-sectional view of a multilayer ceramic capacitor along the line B-B.This is a schematic plan view showing an example of a ceramic green sheet.This is a schematic plan view showing an example of a ceramic green sheet.This is a schematic plan view showing an example of a ceramic green sheet.This is a schematic exploded perspective view showing an example of a mother block.This is a schematic perspective view showing an example of a green chip.This is a diagram (photograph used as a substitute for a drawing) showing the distribution of Al in the cross-section along the C-C line.This is a diagram (photograph used as a substitute for a drawing) showing the distribution of Mg in the cross-section along the C-C line.This is a diagram (photograph used as a substitute for a drawing) showing the distribution of Si in a cross-section along the C-C line. The multilayer ceramic capacitor of the present invention will be described below. However, the present invention is not limited to the following configuration, and can be modified and applied as appropriate without altering the essence of the invention. [Multilayer ceramic capacitors] Figure 1 is a schematic perspective view showing an example of a multilayer ceramic capacitor of the present invention. Figure 2 is a schematic perspective view showing an example of a laminate constituting the multilayer ceramic capacitor shown in Figure 1. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line A-A. Figure 4 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line C-C. In this specification, the stacking direction, width direction, and length direction of the multilayer ceramic capacitor and laminate are defined by the arrows T, W, and L, respectively, in the multilayer ceramic capacitor 1 shown in Figure 1 and the laminate 10 shown in Figure 2. In the embodiment, the stacking (T) direction, width (W) direction, and length (L) direction are orthogonal to each other, but they are not necessarily orthogonal and may intersect each other. The stacking (T) direction is the direction in which a plurality of dielectric layers 20 and a plurality of pairs of first internal electrode layers 21a and second internal electrode layers 21b are stacked. The multilayer ceramic capacitor 1 shown in Figure 1 comprises a laminate 10 and a pair of external electrodes, a first external electrode 51a and a second external electrode 51b, on both end faces of the laminate 10. As shown in Figure 2, the laminate 10 is rectangular or substantially rectangular in shape and has a first main surface 11 and a s