JP-7856203-B2 - Conversion circuit

Inventors

• 渡辺 高元

Assignees

• 株式会社デンソー

Dates

Publication Date

20260511

Application Date

20250916

Claims (6)

1. A conversion circuit that converts voltage (Vin) into numerical data (DTA) using a pulse delay circuit (2) which is configured by connecting a plurality of delay units (DU) in series to output a delayed pulse signal, and outputs a group of delayed pulses from the plurality of delay units, A plurality of latch circuits (21, 22, 23, 24) each comprising a master latch circuit (21m...24m) that holds the state of the output of the delayed pulse group (P1, P2, P3, ..., Pn) output from the pulse delay circuit using mutually different first clocks (CK1...CK4), and a slave latch circuit (21s...24s) that holds the output of the master latch circuit using a second clock (CK1), The system includes an encoder located downstream of the multiple slave latch circuits, and a conversion unit (60; 360) that converts the output data of the multiple slave latch circuits into numerical data, At least two of the plurality of slave latch circuits hold the output data by receiving the second clock based on the first clock as a common input. The plurality of latch circuits are a conversion circuit in which the slave latch circuits are immediately connected in cascading order after the master latch circuit.
2. The conversion circuit according to claim 1, wherein the master latch circuit is configured as a static type that holds the output with a feedback circuit, and the slave latch circuit is configured as a dynamic type that holds the output data without the feedback circuit.
3. The conversion circuit according to claim 1 or 2, wherein the pulse delay circuit is configured by a ring delay line in which the plurality of delay units are arranged in a ring shape.
4. The conversion circuit according to claim 1 or 2, wherein the pulse delay circuit is configured by an open delay line in which the plurality of delay units are arranged in a non-ring shape.
5. The conversion circuit according to any one of claims 1 to 4, wherein the second clock is supplied as a common input to all of the slave latch circuits constituting the plurality of latch circuits.
6. The conversion circuit according to any one of claims 1 to 5, wherein the encoder uses the first clock (CK1, CK2, ..., CKm) or the master clock (CKs) that is the source of the second clock (CK1) as the clock for reading the output data.

Description

This disclosure relates to a conversion circuit that converts an analog input signal into numerical data using a pulse delay circuit comprising multiple pulse delay units connected together, each unit delaying and outputting a pulse signal. Conventionally, A/D conversion circuits have been developed to acquire high-resolution digital values and numerical data while simplifying their configuration (see, for example, Patent Document 1). The A/D conversion device described in Patent Document 1 consists of a pulse delay circuit comprising multiple delay units composed of various gate circuits connected in a dependent configuration. The analog input signal to be converted is supplied to this delay unit as a power supply voltage, thereby configuring it as a time-domain processing type A/D conversion circuit. In the A/D conversion method employed in this Patent Document 1, a pulse delay circuit with delay units arranged in a ring shape transmits the pulse signal. The pulse signal propagates at a speed corresponding to the pulse signal delay time, which depends on the power supply voltage of each delay unit. The analog input signal is converted into numerical data by counting the number of delay units the pulse signal passes through within a predetermined sampling time. This A/D conversion circuit described in Patent Document 1 is called a clock edge shift (CKES) type TAD (Time-A/D converter) A/D conversion circuit and is sometimes abbreviated as CKES-TAD. Japanese Patent Publication No. 2004-007385 Block diagram 1 schematically showing a part of the A/D conversion circuit according to the first embodiment.An electrical diagram schematically showing the clock generation circuit used in the first embodiment.Block diagram 2 schematically showing a part of the A/D conversion circuit according to the first embodiment.Electrical configuration and wiring diagram of the latch circuit according to the first embodimentElectrical diagram of a master-slave type latch circuit used in the first embodimentTime chart illustrating the operation of the latch circuit in the first embodimentElectrical configuration and wiring diagram of a latch circuit in a comparative example.Electrical configuration diagram of a master-slave type latch circuit used in the second embodimentBlock diagram 1 schematically showing a part of the A/D conversion circuit according to the third embodiment.Time chart illustrating the operation of the latch circuit in the third embodimentBlock diagram 2 schematically showing a part of the A/D conversion circuit in the third embodiment. The following describes several embodiments of the conversion circuit with reference to the drawings. In each embodiment, substantially identical or similar parts are denoted by the same or similar reference numerals, for example, the same reference numeral is used for the ones and tens digits, while a different reference numeral is used for the hundreds digit. Descriptions are omitted as needed, and each embodiment focuses on its characteristic features. (First Embodiment) The first embodiment will be described with reference to Figures 1 to 7. Figures 1 to 5 schematically show a time analog to digital converter (TAD) A/D conversion circuit 1. The A/D conversion circuit 1 is constructed using a CMOS manufacturing process inside semiconductor integrated circuit devices such as a microcomputer mounted in an electronic control unit (ECU) of an automobile, a sensor product with digital communication functionality with the ECU, a System on Chip (SoC) of a 5G communication device, and an IoT application system. As shown in Figures 1 and 3, the A/D conversion circuit 1 comprises a pulse delay circuit 2, a clock generation circuit 3, a pulse position digitization unit 4, and an adder 5. This A/D conversion circuit 1 receives an analog input signal Vin output from a sensor or the like, converts this analog input signal Vin into digital numerical data DTA, and outputs it. The pulse position digitization unit 4 is referred to as L&E/S: Latch-&-Encoder and Subtractor. <Explanation of the configuration of pulse delay circuit 2> The pulse delay circuit 2 is constructed by arranging multiple delay units DU in series, each DU inverting and delaying the pulse output in a ring shape, and is called a ring delay line. n is an odd number, for example, 15. The delay unit DU is composed of gates G1 to Gn, each of which delays a pulse by a predetermined delay time Td before outputting it. Therefore, in the following description, one or more delay units will be referred to as "DU," or as "G1"..."Gn." The pulse delay circuit 2 is configured to output the output of each delay unit DU to the pulse position digitization unit 4. Each gate G1 to Gn receives the analog input signal Vin, which is the target of A/D conversion, as the power supply voltage. Each gate G1 to Gn outputs a signal that changes according to this analog input signal Vin. Any gate whose delay time Td changes according to the analog input