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JP-7856240-B2 - Memory operation management in computing systems

JP7856240B2JP 7856240 B2JP7856240 B2JP 7856240B2JP-7856240-B2

Inventors

  • アガルワル，イシュワル
  • クリソス，ジョージ・ザカリアス
  • ローゼル・マルティネス、オスカー

Assignees

  • マイクロソフト テクノロジー ライセンシング，エルエルシー

Dates

Publication Date
20260511
Application Date
20220225
Priority Date
20210524

Claims (9)

  1. A method for managing memory in a computing device having a processor, a first memory adjacent to the processor and configured as a cache for the processor, a second memory separate from the processor and interfaced with the processor, and a memory controller configured to manage the operation of the first and second memories, the method being: The memory controller receives a request from the processor to read data corresponding to the system memory section from the processor's cache; In response to receiving the aforementioned read request, the memory controller performs the following actions: A step of retrieving data from the data portion and metadata from the metadata portion of the first memory from the first memory, wherein the metadata from the metadata portion encodes data location information of a plurality of system memory sections in the first memory and the second memory; The steps include: analyzing the data location information in the metadata extracted from the metadata portion of the first memory to determine whether the first memory currently contains the data corresponding to the system memory section in the received request; The steps include determining that the first memory currently contains data corresponding to the system memory section in the received request, and in response to the received request, transmitting the extracted data from the data portion of the first memory to the processor, method.
  2. This is performed in response to determining that the first memory does not currently contain the data corresponding to the system memory section in the received request. The steps include: further analyzing the data location information in the retrieved metadata in order to identify the memory location in the second memory containing the data corresponding to the system memory section in the received request; The further step of responding to the received request by retrieving the data from the identified memory location in the second memory and providing the retrieved data to the processor, The method according to claim 1.
  3. This is performed in response to determining that the first memory does not currently contain the data corresponding to the system memory section in the received request. The steps include: further analyzing the data location information in the retrieved metadata in order to identify the memory location in the second memory containing the data corresponding to the system memory section in the received request; The steps include: in response to the received request, retrieving the data from the identified memory location in the second memory and providing the retrieved data to the processor; The further step includes writing the retrieved data from the identified memory location in the second memory to the first memory, The method according to claim 1.
  4. This is performed in response to determining that the first memory does not currently contain the data corresponding to the system memory section in the received request. The steps include: further analyzing the data location information in the retrieved metadata in order to identify the memory location in the second memory containing the data corresponding to the system memory section in the received request; The steps of: retrieving the data from the identified memory location in the second memory; The steps include writing the retrieved data from the identified memory location in the second memory to the first memory; The further step includes modifying the metadata in the metadata portion of the first memory to indicate that the data corresponding to the system memory section in the received request is currently in the first memory, The method according to claim 1.
  5. This is performed in response to determining that the first memory does not currently contain the data corresponding to the system memory section in the received request. The steps include: further analyzing the data location information in the retrieved metadata in order to identify the memory location in the second memory containing the data corresponding to the system memory section in the received request; The steps of: retrieving the data from the identified memory location in the second memory; The steps include writing the retrieved data from the identified memory location in the second memory to the first memory; The further step includes writing the data retrieved from the first memory to the identified memory location in the second memory, The method according to claim 1.
  6. This is performed in response to determining that the first memory does not currently contain the data corresponding to the system memory section in the received request. The steps include: further analyzing the data location information in the retrieved metadata in order to identify the memory location in the second memory containing the data corresponding to the system memory section in the received request; The steps of: retrieving the data from the identified memory location in the second memory; The steps include writing the retrieved data from the identified memory location in the second memory to the first memory; The steps include: writing the data retrieved from the first memory to the identified memory location in the second memory; Modify the metadata in the metadata portion of the first memory: The data corresponding to the system memory section in the received request is currently in the first memory. The further step includes indicating that data previously held in the first memory is now located at the identified memory location in the second memory, The method according to claim 1.
  7. The metadata from the metadata portion includes one or more bits; The data location information includes one or more combinations of bits that correspond individually to one of the plurality of system memory sections; Analyzing the aforementioned data location information involves: Identify the combination of one or more bits; This includes determining whether the identified combination corresponds to the system memory section in the received request. The method according to claim 1.
  8. The system memory addressable by the operating system includes several system memory sections, The metadata from the metadata portion includes (1) a combination of bits indicating which system memory sections the first memory holds, and (2) one or more additional combinations of bits, each additional combination of bits indicating a location in the second memory for system memory sections not included in the first memory. The method according to claim 1.
  9. A computing device, Processor and; A first memory adjacent to the processor and configured as a cache for the processor; A second memory, separate from the aforementioned processor and interfaced with the aforementioned processor; The system comprises a memory controller configured to manage the operation of the first and second memories, wherein the memory controller: When the memory controller receives a request from the processor to write a block of data corresponding to the system memory section to the processor's cache: Steps include: extracting metadata from the metadata portion of the first memory from the first memory, wherein the metadata from the metadata portion encodes data location information for a plurality of system memory sections in the first memory and the second memory; The steps include: analyzing the data location information in the metadata extracted from the metadata portion of the first memory to determine whether the first memory currently contains data corresponding to the system memory section in the received request; In response to determining that the first memory currently contains data corresponding to the system memory section in the received request, Write the block of data corresponding to the system memory section to the first memory; The processor has instructions that can be executed by the memory controller to perform a step indicating completion of writing the block of data, The aforementioned memory controller is: In response to determining that the first memory does not currently contain the data corresponding to the system memory section in the received request, The steps include: further analyzing the data location information in the retrieved metadata to identify the memory location in the second memory that currently contains the data corresponding to the system memory section in the received request; The steps include writing the block of data to the identified memory location in the second memory; The processor has additional instructions that can be executed by the memory controller to perform a step indicating completion of writing the block of data, Computing device.

Description

In computing, memory typically refers to the computing component used to store data for immediate access by the central processing unit (CPU) within a computer or other type of computing device. In addition to memory, a computer may also include one or more computer storage devices (e.g., hard disk drives or HDDs) that permanently store data on the computer. In operation, data such as application instructions may first be loaded from the computer storage devices into memory. The CPU can then execute the application instructions loaded into memory to provide computing services such as word processing and online conferencing. This is a schematic diagram illustrating a distributed computing system that implements memory operation management according to an embodiment of the disclosed technology. This is a schematic diagram showing some hardware/software components of the distributed computing system shown in Figure 1, according to embodiments of the disclosed technology. Figures A and B are schematic diagrams illustrating an example of system memory hierarchies according to embodiments of the disclosed technology. A and B are schematic timing diagrams illustrating exemplary read operations using near memory as a swap buffer according to embodiments of the disclosed technology. A and B are schematic timing diagrams illustrating an exemplary write operation using near memory as a swap buffer according to embodiments of the disclosed technology. This computing device is suitable for certain components of the distributed computing system shown in Figure 1. Certain embodiments of systems, devices, components, modules, routines, data structures, and processes for memory operation management are described below. The following description includes specific details of the components to provide a full understanding of certain embodiments of the disclosed technology. Those skilled in the art will also understand that the technology may have additional embodiments. The technology may also be implemented without some of the details of the embodiments described below with reference to Figures 1–6. For example, instead of being implemented in a data center or other suitable distributed computing system, aspects of the memory operation management techniques disclosed herein may also be implemented on personal computers, smartphones, tablets, or other suitable types of computing devices. As used herein, the term “distributed computing system” generally refers to an interconnected computer system having multiple network nodes that interconnect multiple servers or hosts to each other and/or to an external network (e.g., the Internet). The term “network node” generally refers to a physical network device. Exemplary network nodes include routers, switches, hubs, bridges, load balancers, security gateways, or firewalls. “Host” generally refers to a physical computing device. In certain embodiments, a host may be configured to implement, for example, one or more virtual machines, virtual switches, or other suitable virtualization components. For example, a host may include a server having a hypervisor configured to support one or more virtual machines, virtual switches, or other suitable types of virtual components. In other embodiments, a host may be configured to run suitable applications directly on an operating system. Computer networks can, in certain implementations, be conceptually divided into an underlay network and an overlay network implemented on top of it. An “overlay network” generally refers to an abstract network implemented on top of and operating on the underlay network. An underlay network can include multiple physical network nodes interconnected with one another. An overlay network can include one or more virtual networks. A “virtual network” generally refers to an abstraction of a portion of the underlay network within an overlay network. A virtual network can include one or more virtual endpoints, called “tenant sites,” used individually by users or “tenants” to access the virtual network and associated computing, storage, or other appropriate resources. A tenant site can host one or more tenant endpoints (“TEPs”), such as virtual machines. A virtual network can interconnect multiple TEPs on different hosts. Virtual network nodes within an overlay network can be connected to one another by virtual links, each corresponding to one or more network routes along one or more physical network nodes in the underlay network. In other implementations, the computer network may only include an underlay network. Furthermore, as used herein, the term “near memory” generally refers to memory that is physically closer to the processor (e.g., CPU) than other “far memory” located at a certain distance from the processor. For example, near memory may include one or more DDR SDRAM dies incorporated into an integrated circuit (IC) component package with one or more CPU dies via interposers and/or through-silicon vias. In contrast