JP-7856270-B2 - Integrated circuits with non-priority direction curve routing

JP7856270B2JP 7856270 B2JP7856270 B2JP 7856270B2JP-7856270-B2

Inventors

藤村晶

Assignees

ディー・ツー・エス・インコーポレイテッド

Dates

Publication Date: 20260511
Application Date: 20230217
Priority Date: 20230215

Claims (17)

A method for defining IC design for integrated circuits (ICs), A first router is used to define multiple curved paths , each curved path traversing one or more routing layers of a first plurality of routing layers in the IC design so as to be connected at at least two nodes in the IC design, and in defining each curved path, the first router ensures that each curved path is less than or equal to a threshold distance, and each curved path is at least one curved segment that is not a straight line . A method comprising using a second router to define a second plurality of preferred directional linear paths, each traversing one or more of the second plurality of routing layers, to connect at least two nodes in the IC design .
The method according to claim 1, wherein the second plurality of routing layers each have at least a first routing layer and a second routing layer, each having a first priority routing direction and a second priority routing direction, respectively.
The second set of linear paths is for the first set of nets, and each linear path in the second set of linear paths is longer than the threshold distance . The method further includes using the second router to define a third set of preferred directional straight paths for a second set of two or more nets that the first router could not connect through paths traversing the first set of routing layers, Each of the third plurality of preferred directional linear paths traverses one or more of the second plurality of routing layers to connect at least two nodes in the IC design and is shorter than the threshold distance. The method according to claim 1.
The method according to claim 1 , wherein the straight path is formed solely by straight segments .
The method according to claim 1 , wherein the first router imposes a penalty on paths longer than the threshold distance in order to bias against defining paths longer than the threshold distance.
The method according to claim 1 , wherein the first router uses a constraint to prevent the route defined by the first router from becoming longer than the threshold distance.
The method according to claim 1 , further comprising using the first router to define a third plurality of linear paths that traverse the first plurality of routing layers to connect nodes in the IC design .
The method according to claim 7, wherein each path traversing the first plurality of routing layers is less than or equal to the threshold distance.
The method according to claim 8, wherein the route generated by the second router is not a curved route having at least one curved segment.
The method according to claim 1, wherein the first plurality of routing layers include routing layer 3 and routing layer 4, and the second plurality of routing layers include routing layer 5 and routing layer 6.
The method according to claim 1, wherein the second plurality of routing layers include routing layer 1 and routing layer 2.
The method according to claim 1, wherein the first plurality of routing layers include routing layer 1 and routing layer 2.
The method according to claim 12, wherein each of the routing layers 1 and 2 has a plurality of regions having preferred directional linear paths for a predetermined IP (intellectual property) circuit block, and using the first router includes using the first router to define a plurality of curved path segments on the first routing layer and the second routing layer between the regions having the preferred directional linear paths for the IP circuit block.
A system comprising means for carrying out the method described in any one of claims 1 to 13.
A machine-readable medium for storing a program executed by at least one processing unit, wherein the program comprises a set of instructions for carrying out the method described in any one of claims 1 to 13.
It is an electronic device, A set of processing units, An electronic device comprising: a machine-readable medium storing a program that, when executed by at least one processing unit, performs the method according to any one of claims 1 to 13.
A computer program that, when executed by at least one processor, causes a computer to perform the method according to any one of claims 1 to 13 .

Description

An integrated circuit (IC) is a device containing many electronic components such as transistors, resistors, and diodes. These components are often defined on a semiconductor substrate and interconnected by metal wiring and vias to form multiple circuit components such as gates, cells, memory units, arithmetic units, controllers, and decoders. An IC typically includes multiple layers of wiring and vias that interconnect its electronic and circuit components. Some embodiments of the present invention provide integrated circuits (ICs) having a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and a plurality of wiring layers, the plurality of wiring layers including a first set of one or more wiring layers without a preferred wiring direction and a second set of one or more wiring layers having a preferred wiring direction. In some embodiments, the first set of wiring layers includes third and fourth wiring layers, and the second set of wiring layers includes a fifth or more metal layer having consecutive adjacent layers with different (e.g., alternating) preferred wiring directions. In other embodiments, the first set of wiring layers includes a third wiring layer but does not include a fourth wiring layer, and these embodiments have a preferred wiring direction. Also, in some embodiments, the first and second wiring layers belong to the first set, and in other embodiments, the first and second wiring layers belong to the second set. In some embodiments, each preferred routing direction is the Manhattan direction (i.e., horizontal or vertical), and the preferred routing directions of different adjacent layers alternate between horizontal and vertical. In other embodiments, the preferred routing directions include other routing directions (e.g., 45-degree or 60-degree routing directions), and consecutive adjacent layers have different preferred routing directions. In some embodiments, the preferred routing direction on each layer is the direction that includes at least a specific threshold amount (e.g., 90% or 95%) of the routing on that layer. In some embodiments, the non-preferred routing on each layer of a first set of routing layers includes interconnect routing (also called routing connections) that traverses more than eight directions. In some embodiments, each layer of the first set of wiring layers includes straight wires (i.e., wires having only straight segments) and curved wires (i.e., wires having at least one curved segment). In some embodiments, the first set of wiring layers of the IC is used for wire connections shorter than those defined on the second set of wiring layers. In some embodiments, the first set of wiring layers in some embodiments is used for short local connections, and the second set of wiring layers is used for longer connections. In some embodiments, electronic design automation (EDA) tools (e.g., routers and compactors) that define the IC design define paths resulting in metal traces on these layers, while considering preferred and non-preferential directions on each trace layer. In some embodiments, when the first set of trace layers includes a third and/or fourth trace layer, the EDA tool defines NPD curve paths for the third and/or fourth trace layer, but also defines NPD curve paths for the first and second trace layers. However, in some of these embodiments, the first and second trace layers have preferred direction traces in some of their regions, such as regions used for connections required to form electronic components (e.g., transistors) and circuit blocks (e.g., IP blocks) defined on the IC substrate at locations below these regions. In some embodiments, the EDA tool uses unused space on the first and second wiring layers to define NPD straight and/or curved paths, resulting in the formation of NPD straight/curved traces on the corresponding layers of the manufactured IC. The NPD straight/curved traces on the first and second layers reinforce the NPD straight/curved traces on the third and/or fourth wiring layers. In some embodiments, a first set of wiring layers of the IC is used to connect any nets that can be connected via wires on the first set of wiring layers, and a second set of wiring layers is used to connect any nets that cannot be fully connected via wires on the first set of wiring layers. In some of these embodiments, the IC design is based on straight and curved paths defined on the first N layers (where N is an integer greater than 2), but only on straight paths on the next M layers (where M is any integer) of the IC. In some embodiments, the IC design allows for straight and curved paths not only on some of the lower wiring layers, but also on some of the upper wiring layers (e.g., all of the wiring layers, or one or two of the first some lower and upper wiring layers). In some embodiments, a straight path is a path having only one or more straight segments, and a curved path is a path having