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JP-7856391-B2 - Semiconductor equipment

JP7856391B2JP 7856391 B2JP7856391 B2JP 7856391B2JP-7856391-B2

Inventors

  • 小坂 宝
  • 江上 和男

Assignees

  • ローム株式会社

Dates

Publication Date
20260511
Application Date
20210823

Claims (9)

  1. Semiconductor elements and Support member and A bonding layer is interposed between the semiconductor element and the support member, The bonding layer comprises an alloy of a first metal and a second metal. The support member includes a base material and a surface layer interposed between the base material and the bonding layer. The aforementioned surface layer, when viewed in the thickness direction of the support member, protrudes outward from the semiconductor element. The portion of the surface layer that extends beyond the semiconductor element when viewed in the thickness direction has a first surface facing the thickness direction. The bonding layer has a portion located on the substrate side in the thickness direction compared to the first surface, The surface layer has a portion interposed between the bonding layer and the substrate, The first metal is Sn, The aforementioned second metal is Ag, A first layer is interposed between the bonding layer and the semiconductor element and contains a third metal, A semiconductor device comprising a second layer interposed between the bonding layer and the first layer and containing an alloy of the first metal and the third metal .
  2. The semiconductor device according to claim 1 , wherein the bonding layer contains Ag3Sn .
  3. The semiconductor device according to claim 2 , wherein the bonding layer has a composition ratio of Ag of 73% by mass or more.
  4. The semiconductor device according to any one of claims 1 to 3 , wherein the bonding layer is thicker than the second layer.
  5. The semiconductor device according to any one of claims 1 to 4 , wherein the surface layer is thinner than the substrate.
  6. The semiconductor device according to any one of claims 1 to 5 , wherein the surface layer contains Ag.
  7. The semiconductor device according to claim 6 , wherein the substrate contains Cu.
  8. The semiconductor element and at least a part of the support member are covered with a sealing resin, The semiconductor device according to any one of claims 1 to 7 , wherein the support member has a plurality of recesses that are recessed from the first surface.
  9. The semiconductor device according to claim 8 , wherein the recess penetrates the surface layer and reaches the substrate.

Description

This disclosure relates to semiconductor devices . A semiconductor device comprising a lead, a semiconductor element, and solder for joining the lead and the semiconductor element is disclosed. Japanese Patent Publication No. 2020-088319 Figure 1 is a perspective view showing a semiconductor device according to the first embodiment of this disclosure.Figure 2 is a plan view showing a semiconductor device according to the first embodiment of this disclosure.Figure 3 is a front view showing a semiconductor device according to the first embodiment of this disclosure.Figure 4 is a side view showing a semiconductor device according to the first embodiment of this disclosure.Figure 5 is a cross-sectional view taken along the line V-V in Figure 2.Figure 6 is a cross-sectional view along the line VI-VI in Figure 2.Figure 7 is an enlarged cross-sectional view of a main part showing a semiconductor device according to the first embodiment of this disclosure.Figure 8 is an enlarged cross-sectional view of the main part along the line VI-VI in Figure 2.Figure 9 is an enlarged cross-sectional view of the main part along the IX-IX line in Figure 2.Figure 10 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment of this disclosure.Figure 11 is a plan view of a main part showing a method for manufacturing a semiconductor device according to the first embodiment of this disclosure.Figure 12 is an enlarged cross-sectional view of the main part along the line XII-XII in Figure 11.Figure 13 is a plan view of a main part showing a method for manufacturing a semiconductor device according to the first embodiment of this disclosure.Figure 14 is an enlarged cross-sectional view of the main part along the line XIV-XIV in Figure 13.Figure 15 is a cross-sectional view of a key part showing a method for manufacturing a semiconductor device according to the first embodiment of this disclosure.Figure 16 is an enlarged cross-sectional view of a key part showing a method for manufacturing a semiconductor device according to the first embodiment of this disclosure.Figure 17 is an enlarged cross-sectional view of a key part showing a method for manufacturing a semiconductor device according to the first embodiment of this disclosure.Figure 18 is an enlarged cross-sectional view of a key part showing a method for manufacturing a semiconductor device according to the first embodiment of this disclosure.Figure 19 is a cross-sectional view of a main part showing a method for manufacturing a semiconductor device according to the first embodiment of this disclosure.Figure 20 is an enlarged cross-sectional view of a key part showing another example of a method for manufacturing a semiconductor device according to the first embodiment of this disclosure.Figure 21 is a plan view showing a first modified example of a semiconductor device according to the first embodiment of the present disclosure.Figure 22 is an enlarged cross-sectional view of the main part along the line XXII-XXII in Figure 21.Figure 23 is an enlarged cross-sectional view of a key part showing a second modified example of the semiconductor device according to the first embodiment of this disclosure.Figure 24 is a perspective view showing a semiconductor device according to a second embodiment of the present disclosure.Figure 25 is a perspective view showing a first modified example of a semiconductor device according to a second embodiment of the present disclosure.Figure 26 is a perspective view showing a second modified example of a semiconductor device according to the second embodiment of the present disclosure.Figure 27 is a perspective view showing a third modified example of a semiconductor device according to the second embodiment of the present disclosure. Preferred embodiments of this disclosure will be described below with reference to the drawings. The terms "First," "Second," "Third," etc., used in this disclosure are for identification purposes only and are not intended to assign a sequence to the objects. <First Embodiment> Figures 1 to 9 show a semiconductor device according to the first embodiment of the present disclosure. The semiconductor device A1 of this embodiment comprises a support member 1, a conductive member 2, a semiconductor element 3, a bonding layer 4, a wire 5, and a sealing resin 6. Figure 1 is a perspective view showing semiconductor device A1. Figure 2 is a plan view showing semiconductor device A1. Figure 3 is a front view showing semiconductor device A1. Figure 4 is a side view showing semiconductor device A1. Figure 5 is a cross-sectional view along the line V-V in Figure 2. Figure 6 is a cross-sectional view along the line VI-VI in Figure 2. Figure 7 is an enlarged cross-sectional view of a key part of semiconductor device A1. Figure 8 is an enlarged cross-sectional view of a key part along the line VI-VI in Figure 2. Figure 9 is an enlarged cross-sectional view of a key part along the line