Search

JP-7856423-B2 - Semiconductor structure having one or more support structures

JP7856423B2JP 7856423 B2JP7856423 B2JP 7856423B2JP-7856423-B2

Inventors

  • サントス ロドリゲス， フランシスコ ハビエル
  • ハルフマン， マルクス

Assignees

  • インフィネオン テクノロジーズ アーゲー

Dates

Publication Date
20260511
Application Date
20211222
Priority Date
20201228

Claims (14)

  1. Forming a first porous layer on a semiconductor substrate, Forming a first epitaxial layer on the first porous layer, and A method comprising forming a second porous layer from a first portion of the first epitaxial layer, and a support structure from a second portion of the first epitaxial layer.
  2. The method according to claim 1, wherein forming the first porous layer includes applying the first porousization process to the semiconductor substrate, and forming the second porous layer includes applying the second porousization process to the first epitaxial layer.
  3. The method according to claim 1, wherein the support structure includes a plurality of parts.
  4. The method according to claim 1, wherein the support structure includes a loop-shaped structure.
  5. The method according to claim 1, wherein the support structure includes a lattice structure.
  6. The method according to claim 1, wherein the support structure includes a loop-shaped structure arranged around a second structure spaced apart from the loop-shaped structure.
  7. The method according to claim 6, wherein the second structure is a lattice structure.
  8. The method according to claim 1, further comprising forming a second epitaxial layer on the second porous layer.
  9. The method according to claim 8, further comprising forming one or more device structures on and/or within the second epitaxial layer.
  10. The method according to claim 1, further comprising separating the upper portion of the first porous layer from the lower portion of the first porous layer.
  11. Forming a support structure, including a porous structure process. Forming the device layer on the support structure, A method comprising forming one or more device structures on and/or within the device layer , Forming the support structure includes forming a first epitaxial layer to which the porous process is applied. The method wherein the porous formation process porous forms only a portion of the first epitaxial layer, and the support structure includes the non-porous portion of the first epitaxial layer .
  12. The method according to claim 11, further comprising providing a porous layer, wherein the support structure is formed on the porous layer .
  13. The method according to claim 11 or 12 , wherein the non-porous portion includes a plurality of parts.
  14. The method according to any one of claims 11 to 13 , wherein forming the device layer includes forming a second epitaxial layer.

Description

This disclosure relates to the field of support structures for semiconductor wafers. Various types of semiconductor wafers can have varying thicknesses. For example, depending on the diameter, some semiconductor wafers may have a thickness of approximately 700 micrometers for silicon substrates and approximately 370 micrometers for silicon carbide substrates. Thin wafer technology for insulated-gate bipolar transistors (IGBTs) or field-effect transistors (e.g., MOSFETs) allows thin semiconductor wafers to have a thickness of approximately 200 micrometers or less for silicon substrates or approximately 100 micrometers or less for silicon carbide substrates. This is a diagram illustrating an exemplary method for forming one or more support structures for a semiconductor structure.This is a diagram of a semiconductor substrate.This is a diagram of a first porous layer formed on a semiconductor substrate.This is a diagram of the first epitaxial layer formed on the first porous layer.This diagram shows a second porous layer formed from a first portion of the first epitaxial layer and a support structure formed from a second portion of the first epitaxial layer.This is a diagram of a device layer formed on top of a support structure.This is a diagram of one or more device structures formed on and/or within a device layer.This is a diagram of a carrier attached to a semiconductor structure.This is a diagram of a semiconductor structure having a support structure.These are diagrams showing the semiconductor structure from below and from above.This is a diagram of a semiconductor substrate.This is a diagram of the first porous layer formed on a semiconductor substrate.This is a diagram of the first epitaxial layer formed on the first porous layer.This figure shows a second porous layer formed from a first portion of the first epitaxial layer, and a first support structure and a second support structure formed from the second and third portions of the first epitaxial layer.This is a diagram of a device layer formed on top of a support structure.This is a diagram of one or more device structures formed on and/or within a device layer.This is a diagram of a carrier attached to a semiconductor structure.This is a diagram of a semiconductor structure having a support structure.These are diagrams showing the semiconductor structure from below and from above.This is a diagram of a semiconductor substrate.This is a diagram of the first porous layer formed on a semiconductor substrate.This is a diagram of the first epitaxial layer formed on the first porous layer.This figure shows a second porous layer formed from a first portion of the first epitaxial layer, and a first support structure and a second support structure formed from one or more other portions of the first epitaxial layer.This is a diagram of a device layer formed on top of a support structure.This is a diagram of one or more device structures formed on and/or within a device layer.This is a diagram of a carrier attached to a semiconductor structure.This is a diagram of a semiconductor structure having a support structure.This is a diagram of a semiconductor structure having a support structure and metal filling the cavities between the support structures.These are diagrams showing the semiconductor structure from below and from above.These are bottom and top views of a semiconductor structure having support structures and metal filling the cavities between the support structures. The subject matter claimed herein is described with reference to the accompanying drawings, and the same reference numerals are used here to refer to the same elements throughout this specification. In the following description, many specific details are provided for illustrative purposes to ensure a full understanding of the claimed subject matter. However, it will be clear that the claimed subject matter can be implemented without these specific details. In other cases, well-known structures and device structures are shown in block diagram form to facilitate the description of the claimed subject matter. Thin semiconductor wafers can be vulnerable to warping and mechanical damage due to their thinness. For example, mechanical stress on certain areas of a semiconductor wafer (e.g., near the edges) can cause hair-thin cracks and/or destroy the wafer. This can be particularly problematic for thin semiconductor wafers (e.g., when the wafer has a thickness of approximately 200 micrometers or less for silicon substrates and approximately 100 micrometers or less for silicon carbide substrates). To reinforce semiconductor wafers and reduce the likelihood of damage during manufacturing and/or handling, support structures may be created for semiconductor wafers (e.g., they may be attached to or ground into the semiconductor wafer). For example, support structures may be attached to the back surface of the semiconductor wafer. This adds additional complexity to the semiconductor wafer manufact