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JP-7856449-B2 - Information processing device, information processing method, and program

JP7856449B2JP 7856449 B2JP7856449 B2JP 7856449B2JP-7856449-B2

Inventors

  • 古澤 和之

Assignees

  • キヤノン株式会社

Dates

Publication Date
20260511
Application Date
20220302

Claims (9)

  1. A detection means for detecting an event that causes a state transition in at least one bank constituting the DRAM, The system includes a classification means that classifies the state of at least one bank into an operating state, an inoperable state, and a dormant state based on the events detected by the detection means, The classification means is characterized in that, when the detection means detects a first control command for a predetermined bank and a second control command following the first control command, it sets a second operating state interval for which the operating state is classified based on the second control command, based on a first operating state interval for which the operating state is classified based on the first control command.
  2. The information processing apparatus according to claim 1, characterized in that, if the end timing of the first operating state interval is later than the detection timing of the second control command, the classification means sets the end timing of the first operating state interval or a time after the end timing of the first operating state interval as the start timing of the second operating state interval.
  3. The information processing apparatus according to any one of claims 1 to 2, characterized in that the aforementioned operating state is a state in which read or write data access is being performed to the target bank.
  4. The information processing device according to any one of claims 1 to 3, characterized in that the aforementioned inoperable state is a state in which the device is waiting because it cannot perform read or write data access to the bank due to predetermined constraints.
  5. The information processing apparatus according to any one of claims 1 to 4, characterized in that the paused state is neither the operating state nor the non-operating state.
  6. The information processing apparatus according to any one of claims 1 to 5, further comprising control means for displaying the results classified by the classification means on a display means.
  7. The information processing apparatus according to any one of claims 1 to 6, characterized in that the first control command and the second control command are transfer commands.
  8. A detection step in which the detection means detects an event that causes a transition in the state of at least one bank constituting the DRAM, The classification means includes a classification step of classifying the state of at least one bank into an operating state, an inoperable state, and a dormant state based on the events detected in the detection step, The information processing method is characterized in that, in the classification step, when a first control command for a predetermined bank and a second control command following the first control command are detected by the detection means, a second operating state interval is set based on a first operating state interval classified into an operating state based on the first control command, and a second operating state interval is set based on the second control command.
  9. Computers, A detection means for detecting an event that causes a state transition in at least one bank constituting the DRAM, The system includes a classification means that classifies the state of at least one bank into an operating state, an inoperable state, and a dormant state based on the events detected by the detection means, A computer program for causing the classification means to function as an information processing device, characterized in that when a first control command for a predetermined bank and a second control command following the first control command are detected by the detection means, a second operating state interval is set based on a first operating state interval that is classified into an operating state based on the first control command, and the second operating state interval is set based on the second control command.

Description

This invention relates to an information processing apparatus, an information processing method, and a program for analyzing the state of a DRAM. The technology for analyzing the performance of DRAM in system LSIs has been widely used for a long time. Before explaining the performance analysis technology, let's explain DRAM. DRAM stands for Dynamic Random Access Memory, and it is one of the memory devices used in many modern digital devices such as PCs (Personal Computers), smartphones, digital televisions, and digital cameras. SRAM (Static Random Access Memory) is a memory device that is often compared to DRAM. Compared to SRAM, DRAM requires a periodic memory retention operation called a refresh, so it generally consumes more power. On the other hand, its structure makes it easy to achieve high integration, and it has the advantage of being able to provide large capacity at a low cost, so it has been used as a large-capacity memory device for a long time. With the recent increase in pixel counts, such as 4K (image size of approximately 4000 vertical and 2000 horizontal pixels) and 8K (image size of approximately 8000 vertical and 4000 horizontal pixels), the size of digital data for still and moving images continues to increase, and the application range of DRAM remains strong. As DRAM is the main memory device for digital devices, there is a high demand for improved access speed. In response to this demand, DRAM has addressed it through structural advancements such as SDRAM (Synchronous DRAM) and RDRAM (Rambus DRAM), speed improvements through increased clock frequency within the same structure, and various functions that enable high-speed operation. Here, we will explain using SDRAM as an example. SDRAM evolved from SDR (Single Data Rate), which operates only on the rising edge of the clock signal, to DDR (Dual Data Rate), which operates on both the rising and falling edges of the clock signal, theoretically doubling its access rate. Furthermore, DDR, DDR2, DDR3, and DDR4 have evolved, primarily through improvements in clock frequency and capacity, along with the definition of the standards. Low-power versions, designated as LP (Low Power), such as LPDDR2, LPDDR3, LPDDR4, and LPDDR5, have also been standardized. These standards are defined and standardized by the JEDEC Solid State Technology Association, and have evolved to prevent companies manufacturing DRAM from using proprietary standards. As mentioned above, the access performance of SDRAM has evolved, but the control method remains fundamentally the same for all types, including SDR, DDR, and LPDDR, and is controlled by control signals called commands. The control method using commands will be explained using DDR3 as an example. However, as previously stated, the control method is not significantly different for SDR, DDR, DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4, and LPDDR5. Figure 5 shows a list of DDR3 commands. In Figure 5, 501 and 502 indicate the meaning and command notation of the corresponding command when the signals 503 to 513 match that state. The ACT command is used to select the row address of the DRAM. This operation is called activation, and since the memory space at the same row address is treated as a page and preparation for access to the page is made, it is called page open. After selecting the row address with the ACT command, the column address is selected with the RD command and WR command to read and write data to the DRAM memory elements. There are two addresses for selecting memory elements in DRAM: row addresses and column addresses. Basic read and write operations involve first selecting the row address with the ACT command, and then selecting the column address with the RD and WR commands to determine the address of the target memory element. In SDRAM, a method called page mode has been devised to speed up data access, allowing data with different column addresses but the same row address to be read and written sequentially. This enables high-speed access even if the column address is different, as long as the row address is the same. On the other hand, if the row address is different, the activated row address must be returned to a deselected state by an operation called precharge using the PRE command, and then re-activated. This precharge is called page close, in contrast to page open for activation. Due to the structure of DRAM, it is difficult to shorten the time for this series of page close (precharge) and page open (activate) operations, and this has not been significantly shortened even with advancements in standards. Generally, this series of operations is called a page miss. Page misses always occur when the row address changes, so they cannot be avoided. However, structures have been devised to conceal these page misses and improve access efficiency. The mechanism is simple: the entire memory space selected by row and column addresses is constructed in units called banks, and page misses are concealed by impl