JP-7856629-B2 - Hybrid fan-out hybrid density interconnect architecture

Inventors

• ラフール アガルワル
• ブレット ピー． ウィルカーソン
• ラジャ スワミナサン

Assignees

• アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド

Dates

Publication Date

20260511

Application Date

20210812

Priority Date

20201030

Claims (13)

1. It is a semiconductor device , Semiconductor modules and One or more peripheral components outside the semiconductor module, The semiconductor module is further comprising a second interconnection structure for connecting one or more peripheral components, The aforementioned semiconductor module is Two or more semiconductor dies, each semiconductor die having a mixed density input/output interconnect on its die surface, the mixed density input/output interconnect includes a first group interconnect and a second group interconnect, and the first group interconnect has a different density from the second group interconnect, and The system comprises a first interconnection structure coupled to two or more semiconductor dies, The first interconnection structure implements a plurality of die-to-die connection paths having a first density and a plurality of fan-out rerouting paths having a second density different from the first density , The multiple inter-die connection paths and the multiple fan-out rewiring paths are formed together within the same rewiring layer structure. The plurality of inter-die connection paths directly connect the interconnection of the first group of the first semiconductor die among the two or more semiconductor dies to the interconnection of the first group of the second semiconductor die among the two or more semiconductor dies. The plurality of fan-out rerouting paths connect the interconnections of the second group of the first semiconductor die to one or more package interconnections. The second interconnection structure includes interconnection dies connected to the plurality of fan-out rewiring paths, Semiconductor devices .
2. The aforementioned redistribution layer structure is manufactured on the two or more semiconductor dies. A semiconductor device according to claim 1.
3. The redistribution layer structure is manufactured on an interposer coupled to two or more semiconductor dies. A semiconductor device according to claim 1.
4. Each of the two or more semiconductor dies includes a die interface that includes a mixed density input/output interconnection, A semiconductor device according to claim 1.
5. The plurality of interconnections for the inter-die connection path have a finer pitch than the plurality of interconnections for the fan-out rewiring path. The semiconductor device according to claim 4.
6. At least a portion of the fan-out rewiring path terminates at a module interconnect structure, which is adapted to connect the semiconductor module to another device. A semiconductor device according to claim 1.
7. It is a semiconductor device, A semiconductor module including a first interconnection structure that implements a first plurality of connection paths connecting a first die to a second die, wherein the first plurality of connection paths have a first density, A second interconnection structure for connecting the semiconductor module to at least one peripheral component, wherein the second interconnection structure implements a second plurality of connection paths between the first die and the peripheral component, and the second plurality of connection paths have a second density different from the first density, The second interconnection structure includes a wafer-level fan-out redistribution structure manufactured on the interposer. Semiconductor devices.
8. The first interconnection structure includes a redistribution layer manufactured on the first die, the second die, and a mold layer supporting the first die and the second die. The semiconductor device according to claim 7.
9. The first interconnection structure includes a redistribution layer manufactured on an interposer coupled to the first die and the second die. The semiconductor device according to claim 7.
10. The first die includes a die interface that includes a mixed density input/output interconnect, The semiconductor device according to claim 7.
11. The plurality of interconnections for the first plurality of connection paths have a finer pitch than the pitch of the plurality of interconnections for the second plurality of connection paths. A semiconductor device according to claim 10.
12. The second interconnection structure includes interconnection dies within the second plurality of connection paths. The semiconductor device according to claim 7.
13. The interconnect die is connected to the semiconductor module and the peripheral components through a redistribution layer formed on the surface of the second interconnect structure. A semiconductor device according to claim 12.

Description

A System-on-a-Chip (SoC) integrates multiple functional nodes into a single integrated circuit. For example, an SoC may include one or more processor cores, memory interfaces, network interfaces, optical interfaces, digital signal processors, graphics processors, telecommunications components, etc. Traditionally, each node is generated within a monolithic die. However, for various reasons, such as increasing the yield of functional chips or reducing design complexity and cost, it is becoming increasingly common to separate these nodes into individual dies and reconfigure them on a wafer. To achieve the efficiency and performance of monolithic dies, these individual dies must be highly interconnected. As die sizes shrink and/or the number of input/output pins increases, scaling this connectivity is becoming increasingly difficult. This is a block diagram of an exemplary semiconductor device implementing a mixed-density interconnect architecture utilizing hybrid fan-out according to embodiments of the present disclosure.This is a block diagram of an exemplary semiconductor module for a mixed-density interconnect architecture utilizing hybrid fan-out, according to some embodiments of the present disclosure.This is a block diagram of a semiconductor die interface for a mixed-density interconnect architecture utilizing hybrid fan-out, according to some embodiments of the present disclosure.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This is a block diagram of an exemplary semiconductor module for a mixed-density interconnect architecture utilizing hybrid fan-out, according to some embodiments of the present disclosure.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This is a block diagram of an exemplary semiconductor device for a mixed-density interconnect architecture utilizing hybrid fan-out, according to some embodiments of the present disclosure.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments.This is a block diagram of an exemplary semiconductor device for a mixed-density interconnect architecture utilizing hybrid fan-out, according to some embodiments of the present disclosure.This figure shows a portion of an