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JP-7856640-B2 - Semiconductor equipment

JP7856640B2JP 7856640 B2JP7856640 B2JP 7856640B2JP-7856640-B2

Inventors

  • 林口 匡司

Assignees

  • ローム株式会社

Dates

Publication Date
20260511
Application Date
20220502
Priority Date
20210513

Claims (13)

  1. First MOSFET and First-party IGBTs, A first power terminal that conducts to the drain of the first MOSFET and the collector of the first IGBT, A second power terminal that conducts to the source of the first MOSFET and the emitter of the first IGBT, A first Schottky barrier diode electrically connected in parallel to the first MOSFET and the first IGBT, It is equipped with, The drain of the first MOSFET and the collector of the first IGBT are electrically connected. The source of the first MOSFET and the emitter of the first IGBT are electrically connected. The element breakdown voltage of the first MOSFET is greater than that of the element breakdown voltage of the first IGBT. The first MOSFET is composed of SiC, The first IGBT is composed of Si, The inductance of the first conduction path from the drain of the first MOSFET to the first power terminal is smaller than the inductance of the second conduction path from the collector of the first IGBT to the first power terminal. The first Schottky barrier diode is composed of SiC, The length of the third conduction path from the first Schottky barrier diode to the first power terminal is greater than the length of the first conduction path and less than the length of the second conduction path. A semiconductor device in which the length of the second conduction path is greater than the length of the first conduction path .
  2. The second MOSFET, Second-generation IGBTs, Furthermore, The drain of the second MOSFET and the collector of the second IGBT are electrically connected. The source of the second MOSFET and the emitter of the second IGBT are electrically connected. The semiconductor device according to claim 1 , wherein the element breakdown voltage of the second MOSFET is greater than the element breakdown voltage of the second IGBT.
  3. The above-mentioned second MOSFET is composed of SiC, The semiconductor device according to claim 2 , wherein the second IGBT is composed of Si.
  4. The device further comprises a third power terminal that conducts to the source of the second MOSFET and the emitter of the second IGBT, The second power terminal is electrically connected to the drain of the second MOSFET and the collector of the second IGBT. The semiconductor device according to claim 2 , wherein the inductance of the fourth conduction path from the source of the second MOSFET to the first power terminal is smaller than the inductance of the fifth conduction path from the emitter of the second IGBT to the first power terminal.
  5. The semiconductor device according to claim 4 , further comprising a second Schottky barrier diode electrically connected in parallel with the second MOSFET and the second IGBT.
  6. The semiconductor device according to claim 5 , wherein the second Schottky barrier diode is composed of SiC.
  7. The semiconductor device according to claim 5 , wherein the length of the sixth conduction path from the second Schottky barrier diode to the first power terminal is greater than the length of the fourth conduction path and less than the length of the fifth conduction path.
  8. The first conductor to which the first power terminal is connected, The second conductor to which the second power terminal is connected, The third conductor to which the third power terminal is connected, It also has the following features: The first conductor includes a first pad portion that is electrically connected to the drain of the first MOSFET and the collector of the first IGBT. The second conductor includes a second pad portion that is electrically connected to the source of the first MOSFET, the emitter of the first IGBT, the drain of the second MOSFET, and the collector of the second IGBT. The semiconductor device according to any one of claims 4 to 7 , wherein the third conductor includes a third pad portion that conducts to the source of the second MOSFET and the emitter of the second IGBT.
  9. Each of the first MOSFET and the second MOSFET has a vertical structure in which the drain and the source are arranged apart in the respective thickness direction. The semiconductor device according to claim 8 , wherein each of the first IGBT and the second IGBT has a vertical structure in which the collector and emitter are spaced apart in the respective thickness direction.
  10. A first connecting member electrically connects the source and the second pad portion of the first MOSFET, The device further comprises a second connecting member that electrically connects the emitter of the first IGBT and the second pad portion, The semiconductor device according to claim 9 , wherein the drain of the first MOSFET and the collector of the first IGBT are electrically connected to the first pad portion.
  11. A third connecting member electrically connects the source and the third pad portion of the second MOSFET, A fourth connecting member electrically connects the emitter of the second IGBT and the third pad portion, Furthermore, The semiconductor device according to claim 10 , wherein the drain of the second MOSFET and the collector of the second IGBT are electrically connected to the second pad portion.
  12. The first MOSFET and the first IGBT are arranged along a first arrangement direction that intersects the thickness direction of the first pad portion. The second MOSFET and the second IGBT are arranged along a second arrangement direction that intersects the thickness direction of the second pad portion. The semiconductor device according to claim 11 , wherein the first arrangement direction and the second arrangement direction are the same direction.
  13. The semiconductor device according to claim 12, wherein the first power terminal and the third power terminal are located opposite the first IGBT to the first MOSFET in the first arrangement direction, and opposite the second IGBT to the second MOSFET in the second arrangement direction.

Description

This disclosure relates to semiconductor devices. Conventionally, semiconductor devices equipped with switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are known. For example, Patent Document 1 discloses a power module (semiconductor device) equipped with either a MOSFET or an IGBT switching element. Such power modules are used, for example, in inverters, and perform power conversion through the switching operation of the switching elements. Japanese Patent Publication No. 2018-174252 Figure 1 is a perspective view showing a semiconductor device according to the first embodiment.Figure 2 is a plan view showing a semiconductor device according to the first embodiment, in which the sealing member is indicated by dashed lines.Figure 3 is a cross-sectional view along the line III-III in Figure 2.Figure 4 is a cross-sectional view along the line IV-IV in Figure 2.Figure 5 is a cross-sectional view taken along the line V-V in Figure 2.Figure 6 shows an example of the circuit configuration of a semiconductor device according to the first embodiment.Figure 7 is a perspective view showing a semiconductor device according to the second embodiment.Figure 8 is a perspective view of Figure 7, with some parts of the case (top panel) and resin components omitted.Figure 9 is a plan view showing a semiconductor device according to the second embodiment, in which part of the case (top plate) and resin members are omitted.Figure 10 is a cross-sectional view taken along the line X-X in Figure 9.Figure 11 is a cross-sectional view along the line XI-XI in Figure 9.Figure 12 is a cross-sectional view along the line XII-XII in Figure 9.Figure 13 is a cross-sectional view along the line XIII-XIII in Figure 9.Figure 14 is a perspective view showing a semiconductor device according to the third embodiment.Figure 15 is a plan view showing a semiconductor device according to the third embodiment, in which the sealing member is indicated by dashed lines.Figure 16 is a plan view of Figure 15, with the main metal layer, multiple external terminals, multiple connecting members, and resin members omitted.Figure 17 is a plan view of Figure 16 with the insulating substrate omitted.Figure 18 is a cross-sectional view along the line XVIII-XVIII in Figure 15.Figure 19 is a cross-sectional view along the line XIX-XIX in Figure 15.Figure 20 is a perspective view showing a semiconductor device according to the fourth embodiment.Figure 21 is a perspective view of Figure 20, with the sealing member omitted.Figure 22 is a plan view showing a semiconductor device according to the fourth embodiment, in which the sealing member is indicated by dashed lines.Figure 23 is a cross-sectional view along the line XXIII-XXIII in Figure 22.Figure 24 is a cross-sectional view along the line XXIV-XXIV in Figure 22.Figure 25 is a plan view showing a modified semiconductor device, in which the sealing member is indicated by dashed lines.Figure 26 is a plan view showing a modified semiconductor device, in which the sealing member is indicated by dashed lines. Preferred embodiments of the semiconductor devices of this disclosure will be described below with reference to the drawings. Hereafter, identical or similar components will be denoted by the same reference numerals, and redundant descriptions will be omitted. The terms "first," "second," "third," etc., used in this disclosure are used merely as labels and are not necessarily intended to assign a sequence to the objects. In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is located on object B in contact with object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, unless otherwise specified, "object A overlaps with object B when viewed from a certain direction" includes both "object A overlapping with all of object B" and "object A overlapping with a part of object B." Figures 1 to 6 show a semiconductor device A1 according to the first embodiment. The semiconductor device A1 comprises two switching circuits 1 and 2, a support member 3, a plurality of external terminals, a plurality of connecting members, and a sealing member 6. The plurality of external terminals include a plurality of power terminals 41, 42, and 43, and a plurality of signal terminals 44A, 44B, 45A, 45B, and 49. The plurality of conn