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JP-7856656-B2 - Semiconductor equipment

JP7856656B2JP 7856656 B2JP7856656 B2JP 7856656B2JP-7856656-B2

Inventors

  • 谷川 昂平

Assignees

  • ローム株式会社

Dates

Publication Date
20260511
Application Date
20220715
Priority Date
20210810

Claims (17)

  1. A conductive substrate having a main surface facing one side in the thickness direction and a back surface facing the opposite side from the main surface, A plurality of first semiconductor elements having a switching function are bonded to the main surface, The system comprises a first conductive member that constitutes a path for the main circuit current switched by the plurality of first semiconductor elements, The first conductive member includes a first wiring section, a second wiring section, a third wiring section, a fourth wiring section, and a fifth wiring section. The first wiring portion extends in a first direction perpendicular to the thickness direction, The second wiring portion is separated from the first wiring portion in a second direction perpendicular to both the thickness direction and the first direction, and extends in the first direction. The third wiring section is connected to both the first wiring section and the second wiring section and extends in the two directions. The fourth wiring section is separated from the third wiring section in the first direction and is connected to both the first and second wiring sections, extending in the second direction. The fifth wiring section is located between the first wiring section and the second wiring section in the second direction and is connected to both the third wiring section and the fourth wiring section. The third wiring section is connected to the plurality of first semiconductor elements, and is a semiconductor device.
  2. The semiconductor device according to claim 1, wherein the first conductive member is made of a metal plate.
  3. The third wiring portion has a plurality of concave regions that protrude to the other side in the thickness direction, The semiconductor device according to claim 2, wherein each of the plurality of concave regions is joined to any of the plurality of first semiconductor elements.
  4. The semiconductor device according to claim 3, wherein the fourth wiring portion has a plurality of convex regions that protrude to one side in the thickness direction.
  5. The semiconductor device according to claim 4, wherein the plurality of concave regions and the plurality of convex regions are equal in position in the second direction.
  6. The semiconductor device according to claim 3, wherein at least one of the plurality of concave regions has a slit extending in the first direction.
  7. The conductive substrate includes a first conductive portion and a second conductive portion arranged spaced apart from each other on one side and the other side in the first direction. The semiconductor device according to claim 3, wherein the plurality of first semiconductor elements are electrically joined to the first conductive portion.
  8. A plurality of second semiconductor elements electrically connected to the second conductive portion and having a switching function, The semiconductor device according to claim 7, further comprising a second conductive member made of a metal plate material, which is connected to the plurality of second semiconductor elements and the first conductive portion.
  9. The semiconductor device according to claim 8, wherein the fourth wiring portion overlaps the plurality of second semiconductor elements when viewed in the thickness direction.
  10. The fourth wiring section has a plurality of convex regions that protrude to one side in the thickness direction, The semiconductor device according to claim 9, wherein the plurality of convex regions and the plurality of second semiconductor elements overlap each other when viewed in the thickness direction.
  11. The semiconductor device according to claim 8 or 9, wherein at least one of the plurality of concave regions has a slit extending in the first direction.
  12. A first terminal is positioned on one side in the first direction relative to the second conductive portion and is connected to the first wiring portion, A second terminal is positioned on one side in the first direction relative to the second conductive portion and is connected to the second wiring portion, The third terminal connected to the first conductive part, The semiconductor device according to any one of claims 8 to 10 , further comprising a fourth terminal connected to the second conductive portion.
  13. The semiconductor device according to claim 12, wherein the first terminal, the second terminal, and the fourth terminal overlap each other when viewed in the second direction.
  14. The semiconductor device according to any one of claims 8 to 10 , wherein the second conductive member overlaps with the fifth wiring portion when viewed in the thickness direction.
  15. The semiconductor device according to any one of claims 8 to 10 , wherein the plurality of first semiconductor elements and the plurality of second semiconductor elements overlap each other when viewed in the first direction.
  16. The semiconductor device according to any one of claims 2 to 10 , wherein the first conductive member contains copper.
  17. The semiconductor device according to any one of claims 1 to 10 , wherein the fifth wiring portion includes a plurality of wiring portions that are spaced apart in the second direction and each extends in the first direction.

Description

This disclosure relates to semiconductor devices. Conventionally, semiconductor devices equipped with power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are known. Such semiconductor devices are mounted in various electronic devices, from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 discloses a conventional semiconductor device (power module). The semiconductor device described in Patent Document 1 comprises a semiconductor element and a support substrate. The semiconductor element is, for example, an IGBT made of Si (silicon). The support substrate supports the semiconductor element. The support substrate includes an insulating substrate and conductive layers laminated on the main surface and back surface of the substrate. The substrate is, for example, made of ceramic. Each conductive layer is made of, for example, Cu (copper), and a semiconductor element is bonded to one of the conductive layers. Japanese Patent Publication No. 2015-220382 Figure 1 is a perspective view showing a semiconductor device according to the first embodiment of this disclosure.Figure 2 is a perspective view of Figure 1, with the sealing resin omitted.Figure 3 is a perspective view of Figure 2, with the first conductive member omitted.Figure 4 is a plan view of the semiconductor device shown in Figure 1.Figure 5 is a plan view of Figure 4, with the sealing resin indicated by dashed lines.Figure 6 is a right side view of the semiconductor device shown in Figure 1, with the sealing resin indicated by dashed lines.Figure 7 is a partially enlarged view of a portion of Figure 5, with the sealing resin omitted.Figure 8 is a plan view of the first conductive member.Figure 9 is a plan view of Figure 5, but with the sealing resin and the first conductive member omitted, and the second conductive member indicated by dashed lines.Figure 10 is a right side view of the semiconductor device shown in Figure 1.Figure 11 is a bottom view of the semiconductor device shown in Figure 1.Figure 12 is a cross-sectional view along the line XII-XII in Figure 5.Figure 13 is a cross-sectional view along the line XIII-XIII in Figure 5.Figure 14 is a magnified view of a portion of Figure 13.Figure 15 is a magnified view of a portion of Figure 13.Figure 16 is a cross-sectional view along the line XVI-XVI in Figure 5.Figure 17 is a cross-sectional view along the line XVII-XVII in Figure 5.Figure 18 is a cross-sectional view along the line XVIII-XVIII in Figure 5.Figure 19 is a plan view similar to Figure 7 (with the sealing resin omitted) showing a semiconductor device according to a modified example of the first embodiment.Figure 20 is a cross-sectional view along the line XX-XX in Figure 19.Figure 21 is a cross-sectional view along the line XXI-XXI in Figure 19. Preferred embodiments of this disclosure will be described in detail below with reference to the drawings. The terms "First," "Second," "Third," etc., used in this disclosure are merely labels and are not necessarily intended to assign a sequence to the objects. In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is located on object B in contact with object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, unless otherwise specified, "object A overlaps with object B when viewed in a certain direction" includes both "object A overlapping with all of object B" and "object A overlapping with a part of object B." Figures 1 to 18 show a semiconductor device according to the first embodiment of the present disclosure. The semiconductor device A1 of this embodiment comprises a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a conductive substrate 2, a support substrate 3, a first terminal 41, a second terminal 42, a plurality of third terminals 43, a fourth terminal 44, a plurality of control terminals 45, a control terminal support 48, a first conductive member 5, a second conductive member 6, and a sealing resin 8. Figure 1 is a perspective view showing semiconductor device A1. Figure 2 is a perspective view of Figure 1 with the sealing resin 8 omitted. Figure 3 is a perspective view of Figure 2 with the first conductive member 5 omitted. Figure 4 is a plan view showing semiconduc