JP-7856742-B2 - Cryptographic systems for post-quantum cryptographic operations

JP7856742B2JP 7856742 B2JP7856742 B2JP 7856742B2JP-7856742-B2

Inventors

マルック－ユハニ・オラヴィ・サーリネン

Assignees

ピーキューシールド・リミテッド

Dates

Publication Date: 20260511
Application Date: 20220714
Priority Date: 20210715

Claims (20)

A cryptographic system that performs post-quantum cryptographic operations on a communicationally coupled computing system, wherein the cryptographic system is isolated from the communicationally coupled computing system. A bus interface set for connecting the cryptographic system to one or more system buses of the computing system in a communicative manner, Cryptographic numerical processing unit and, A control device comprising at least one processor and memory for controlling the cryptographic numerical arithmetic device, wherein the control device is communicably coupled to the bus interface set via a first internal bus and communicably coupled to the cryptographic numerical arithmetic device via a second internal bus, and the first internal bus and the second internal bus do not allow access to the internal cryptographic data of the cryptographic numerical arithmetic device during the encryption operation, It is equipped with, The aforementioned cryptographic numerical processing device A matrix memory for storing multidimensional arrays of data, An address generator configured to receive control signals from the control device and control access to data in the matrix memory, An arithmetic unit that performs a defined set of arithmetic operations on data in the matrix memory accessed using the address generator, A sorting device configured to generate a random bit sequence, wherein the sorting device is controlled by the control device and is communicatively coupled to the arithmetic unit, Equipped with, The cryptographic system is configured to perform masked arithmetic calculations by decomposing a confidential data value into a plurality of data shares, and the control device is configured to control the arithmetic unit and the address generator to apply at least one of the defined set of arithmetic operations as a plurality of independent linear operations for each of the plurality of data shares.
The cryptographic system includes a masked operating mode, in which the masked operating mode, The bus interface set receives instructions from the communicably coupled computing system to perform masked arithmetic calculations as a single atomic operation, The control device determines a first set of control signals for controlling access to the data in the matrix memory, and a second set of control signals for controlling the operation of at least one of the arithmetic units for performing the masked arithmetic calculations. The confidential data value stored in the matrix memory is decomposed into a plurality of masked data shares by applying one or more random bit sequences from the sorting device to the confidential data value, The repeated application of the at least one operation to each of the plurality of data shares using the arithmetic unit to perform the masked arithmetic calculation, wherein the at least one operation is applied as a plurality of independent linear operations. The cryptographic system according to claim 1, configured to perform the following:
In the masked operating mode, the encryption system, To obtain encrypted confidential data values via the aforementioned bus interface set, The process involves decrypting the encrypted confidential data values and storing the decrypted data values in the matrix memory in order to decompose them into the masked data shares. It is configured to do the following: The cryptographic system according to claim 2, wherein the result of at least one of the operations is exported in an encrypted form only to the communicably coupled computing system.
The cryptographic system according to claim 1, wherein the sorting device performs ASCON sorting.
The cryptographic system according to claim 1, wherein the control device comprises a set of unconditional instructions stored in the memory and executed by the processor.
The sorting device is, It includes an extensible output function (XOF) device that applies cryptographic operations to generate an infinitely long output stream, The cryptographic system according to any one of claims 1 to 5, wherein the XOF device is controlled by the control device and is communicably coupled to the arithmetic unit.
The cryptographic system according to claim 6, wherein the XOF device is configured to perform one or more of the following operations: cryptographic absorption, cryptographic squeeze, cryptographic sampling, and cryptographic random masking.
The cryptographic system according to claim 6, wherein the XOF device comprises an n-bit cryptographic state divided into multiple data shares for masked arithmetic calculations.
The cryptographic system according to claim 1, wherein the cryptographic system is configured to compute a hash-based signature by repeatedly hashing the data stored in the matrix memory.
The cryptographic system according to claim 6, wherein the cryptographic system is configured to compute one or more Winternitz hash chains and Merkle tree data.
The aforementioned cryptographic system, A key establishment function that includes one or more encryption and decryption functions, A digital signature function that includes one or more of the following: digital signature generation and digital signature verification, The cryptographic system according to claim 1, configured to perform one or more of the following: stateful hash-based signing and
The aforementioned cryptographic system, Implement one or more of the lattice post-quantum key establishment functions and the codebase post-quantum key establishment function, Implement one or more of the following: lattice post-quantum digital signature function, code-based post-quantum digital signature function, hash-based post-quantum digital signature function, and multivariate post-quantum digital signature function. Implementing a hierarchical signature system function, The cryptographic system according to claim 11, configured to perform the following:
The cryptographic system according to claim 1, wherein the arithmetic processing unit receives control data from the control device indicating an operation selected for execution, and comprises an arithmetic processing pipeline unit that executes the selected operation as a plurality of stages over time.
The cryptographic system according to claim 13, wherein the plurality of stages comprises a plurality of parallel processing streams, and the plurality of parallel processing streams receive data accessed from the matrix memory.
The cryptographic system according to claim 1, wherein the processor of the control device is configured to receive vector instructions via the bus interface set and convert the vector instructions into control instructions for the vector operation of the cryptographic numerical arithmetic unit.
The aforementioned bus interface set is A set of control registers writable by at least one processor of the communicationally coupled computing system, A set of cryptographic registers for securely encrypted data, The cryptographic system according to claim 1, comprising:
The cryptographic system according to claim 1, wherein the control device is configured to convert from a first masking format to a second masking format.
The cryptographic system according to claim 1, wherein the control device is configured to implement one or more of Boolean masking and arithmetic operation masking.
A method for operating a cryptographic system, wherein the cryptographic system is isolated from a communicationally coupled computing system, and the method is The encryption system receives instructions from the communicably coupled computing system to perform masked arithmetic calculations as a single atomic operation via the bus interface set of the encryption system, The control device of the cryptographic system, which comprises at least one processor and memory, accesses the instructions written to the bus interface set, The control device determines a first set of control signals for controlling access to data in the matrix memory of the cryptographic system, and a second set of control signals for controlling the operation of at least one arithmetic unit of the cryptographic system to perform the masked arithmetic calculations. The process involves applying one or more random bit sequences from the sorting device of the cryptographic system to the confidential data value, thereby decomposing the confidential data value stored in the matrix memory into a plurality of masked data shares. Using the first set of control signals and the second set of control signals, the arithmetic unit is used to perform the masked arithmetic calculation, repeatedly applying the at least one operation to each of the plurality of data shares, wherein the at least one operation is applied as a plurality of independent linear operations, Includes, The method wherein, at least during the disassembly and the repeated application, the control device is prevented from accessing the contents of the matrix memory or the arithmetic unit.
Exporting the non-confidential result of the masked arithmetic calculation to the communicationally coupled computing system via the bus interface set of the cryptographic system, If the masked arithmetic calculation provides a confidential result, the method includes encrypting the confidential result before exporting it. The method according to claim 19, including the method described in claim 19.

Description

This invention relates to cryptographic hardware, and more particularly, to a cryptographic system for performing cryptographic operations. This cryptographic system can be used as part of a post-quantum cryptography system on a chip. This cryptographic system can be used to perform cryptographic computations in a communicatively coupled computing system, and can operate, for example, as a cryptographic module for a computing board. Methods for operating the cryptographic system are also described. In particular, methods and systems relating to masking and side-channel security are provided. Recently, the number of devices connected to computer networks has been exponentially increasing. For example, internet connectivity is extending beyond computing devices such as desktop and laptop computers to embedded systems in everyday items like automobiles, light bulbs, refrigerators, medical devices, thermostats, and monitoring systems. Telecommunication links enable many low-cost computing devices worldwide to report sensor data and/or be controlled. One problem with such connected devices is their vulnerability to attacks and malicious control. For instance, hundreds or thousands of embedded devices could be compromised by malicious actors and used to execute distributed denial-of-service attacks. Often, control of such devices can be easily gained due to poor or limited implementation of cryptographic protocols. As the number and proliferation of such connected devices increase, unresolved issues remain regarding how to protect them. Another consideration when protecting connected computing devices is the potential for future attacks using quantum computing. For many years, quantum computers were merely a theoretical interest. However, research and implementation of quantum computers are rapidly advancing. Currently, 50-qubit and 72-qubit quantum computers are available, and many research groups are actively working on developing higher-qubit machines. Given the potential for quantum computing to become a reality in the future, recent research has shown that many widely known public-key cryptography systems could be broken by sufficiently powerful quantum computers. When implementing cryptographic functions, especially "post-quantum" secure ones, a challenge arises: many of these functions are resource-intensive. For example, many cryptographic functions involve complex mathematical functions using long bit lengths. These typically consume numerous processor cycles, hindering implementation in low-resource embedded devices. Furthermore, as end-to-end encryption of both data and communications becomes more common, these cryptographic functions also need to be executed quickly and repeatedly. Being secure often means being slow. WO2021/032946A1, incorporated herein by reference, describes a coprocessor that enables a processing unit to efficiently perform cryptographic operations. The coprocessor has an arithmetic unit configured to perform discrete binary operations using bit sequences loaded from memory. The coprocessor may be configured to compute certain functions, including low-level building blocks for cryptographic operations, quickly and with low power. Such functions may include Boolean logic and integer operations. The coprocessor has a set of control registers writable by the processing unit to control the coprocessor. To enable flexible operation, the addresses of one or more sources and destinations may be computed by the coprocessor. The coprocessor can enable the rapid computation of many advanced cryptographic operations, including “post-quantum” secure cryptographic operations. The cryptographic coprocessors described in WO2021/032946A1 may be protected using security fuses and/or side-channel attack countermeasures. However, WO2021/032946A1 does not detail how these may be implemented and/or integrated within flexible cryptographic processing circuits. US2010/115237A1, incorporated herein by reference, describes a coprocessor having one or more application engines that can be dynamically configured for a desired personality. For example, an application engine may be dynamically configured for one of several different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The coprocessor further includes common infrastructure common across different personalities, such as instruction decoding infrastructure, memory management infrastructure, system interface infrastructure, and/or a scalar processing unit (having a base set of instructions). Thus, the coprocessor's common infrastructure remains consistent across various personalities, while the coprocessor's personality can be dynamically changed (by reconfiguring one or more of its application engines). US2010/115237A1 describes how a predefined instruction set may be designed to handle cryptographic operations, but does not describe specific ada