JP-7856814-B2 - Semiconductor equipment

JP7856814B2JP 7856814 B2JP7856814 B2JP 7856814B2JP-7856814-B2

Inventors

山崎舜平

Assignees

株式会社半導体エネルギー研究所

Dates

Publication Date: 20260511
Application Date: 20250501
Priority Date: 20150717

Claims (3)

A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, It has a capacitive element, The gate of the first transistor, one of the source and drain of the second transistor, and one electrode of the capacitive element are electrically connected. A first conductive layer is provided, having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor. A first insulating layer is provided, having a region located above the first conductive layer and a region located below the channel formation region of the second transistor. An oxide semiconductor layer having a channel formation region for the second transistor is provided, A second conductive layer is provided, which functions as one electrode of the capacitive element. A third conductive layer is provided, having a region located above the second conductive layer and functioning as the other electrode of the capacitive element. A fourth conductive layer is provided, having a region located below the oxide semiconductor layer and having a region that functions as the first gate electrode of the second transistor. A fifth conductive layer is provided, having a region located above the oxide semiconductor layer and having a region that functions as the second gate electrode of the second transistor. A second insulating layer is provided, having a region in contact with the fifth conductive layer. The second conductive layer is located above the channel formation region of the first transistor and has a region that overlaps with the channel formation region of the first transistor. The second conductive layer is located above the oxide semiconductor layer and has a region that overlaps with the oxide semiconductor layer. The third conductive layer has a region that overlaps with the channel formation region of the first transistor and a region that overlaps with the channel formation region of the second transistor. The second insulating layer has a first opening and a second opening, The second conductive layer is electrically connected to the oxide semiconductor layer through the first opening. The second conductive layer is electrically connected to the first conductive layer through the second opening. The first opening has a region that overlaps with the oxide semiconductor layer and a region that overlaps with the third conductive layer, and does not overlap with the first conductive layer. The second opening has a region that overlaps with the third conductive layer and does not overlap with the oxide semiconductor layer. The semiconductor device wherein the fourth conductive layer has a region located above the first insulating layer.
A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, It has a capacitive element, The gate of the first transistor, one of the source and drain of the second transistor, and one electrode of the capacitive element are electrically connected. A first conductive layer is provided, having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor. A first insulating layer is provided, having a region located above the first conductive layer and a region located below the channel formation region of the second transistor. An oxide semiconductor layer having a channel formation region for the second transistor is provided, A second conductive layer is provided, which functions as one electrode of the capacitive element. A third conductive layer is provided, having a region located above the second conductive layer and functioning as the other electrode of the capacitive element. A fourth conductive layer is provided, having a region located below the oxide semiconductor layer and having a region that functions as the first gate electrode of the second transistor. A fifth conductive layer is provided, having a region located above the oxide semiconductor layer and having a region that functions as the second gate electrode of the second transistor. A second insulating layer is provided, having a region in contact with the fifth conductive layer. The second conductive layer is located above the channel formation region of the first transistor and has a region that overlaps with the channel formation region of the first transistor. The second conductive layer is located above the oxide semiconductor layer and has a region that overlaps with the oxide semiconductor layer. The third conductive layer has a region that overlaps with the channel formation region of the first transistor and a region that overlaps with the channel formation region of the second transistor. The second insulating layer has a first opening and a second opening, The second conductive layer is electrically connected to the oxide semiconductor layer through the first opening. The second conductive layer is electrically connected to the first conductive layer through the second opening. The first opening has a region that overlaps with the oxide semiconductor layer and a region that overlaps with the third conductive layer, and does not overlap with the first conductive layer. The second opening has a region that overlaps with the third conductive layer and does not overlap with the oxide semiconductor layer. The fourth conductive layer has a region located above the first insulating layer, In a cross-sectional view of the second transistor in the channel width direction , a portion of the lower surface of the fifth conductive layer is located below the lower surface of the oxide semiconductor layer in the semiconductor device.
A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, It has a capacitive element, The gate of the first transistor, one of the source and drain of the second transistor, and one electrode of the capacitive element are electrically connected. A first conductive layer is provided, having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor. A first insulating layer is provided, having a region located above the first conductive layer and a region located below the channel formation region of the second transistor. An oxide semiconductor layer having a channel formation region for the second transistor is provided, A second conductive layer is provided, which functions as one electrode of the capacitive element. A third conductive layer is provided, having a region located above the second conductive layer and functioning as the other electrode of the capacitive element. A fourth conductive layer is provided, having a region located below the oxide semiconductor layer and having a region that functions as the first gate electrode of the second transistor. A fifth conductive layer is provided, having a region located above the oxide semiconductor layer and having a region that functions as the second gate electrode of the second transistor. A second insulating layer is provided, having a region in contact with the fifth conductive layer. The second conductive layer is located above the channel formation region of the first transistor and has a region that overlaps with the channel formation region of the first transistor. The second conductive layer is located above the oxide semiconductor layer and has a region that overlaps with the oxide semiconductor layer. The third conductive layer has a region that overlaps with the channel formation region of the first transistor and a region that overlaps with the channel formation region of the second transistor. The second insulating layer has a first opening and a second opening, The second conductive layer is electrically connected to the oxide semiconductor layer through the first opening. The second conductive layer is electrically connected to the first conductive layer through the second opening. The first opening has a region that overlaps with the oxide semiconductor layer and a region that overlaps with the third conductive layer, and does not overlap with the first conductive layer. The second opening has a region that overlaps with the third conductive layer and does not overlap with the oxide semiconductor layer. The fourth conductive layer has a region located above the first insulating layer, In a cross-sectional view of the second transistor in the channel width direction , a portion of the lower surface of the fifth conductive layer is located below the lower surface of the oxide semiconductor layer. A semiconductor device having a channel length direction of the first transistor that is aligned with the channel length direction of the second transistor.

Description

The present invention relates to a product, a method, or a method of manufacturing; or to a process, a machine, a manufacture, or a composition of matter. In particular, the present invention relates to, for example, semiconductor devices, display devices, light-emitting devices, energy storage devices, imaging devices, methods for driving them, or methods for manufacturing them. In particular, one aspect of the present invention relates to a semiconductor device or a method for manufacturing the same. In this specification, the term "semiconductor device" refers to all devices that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are examples of semiconductor devices. Furthermore, memory devices, Display devices and electronic devices may include semiconductor devices. A technology that constructs transistors using semiconductor films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are also gaining attention as other materials. For example, Patent Document 1 discloses a transistor using an amorphous oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn) as the active layer of the transistor. Furthermore, a method for manufacturing a transistor in which a conductive layer is formed on an oxide semiconductor layer and then heat-treated to reduce the resistance of the oxide semiconductor layer is disclosed in Patent Document 2 and Non-Patent Documents. Japanese Patent Publication No. 2006-165528Japanese Patent Publication No. 2013-175710 2015 Symposium on VLSI Technology Digest of Technical Papers T214-T215 Top view and cross-sectional view illustrating a transistor.Cross-sectional view and band diagram of an oxide semiconductor layer transistor.A diagram illustrating the ALD film deposition principle.ALD device overview diagram.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.Top view and cross-sectional view illustrating a transistor.Top view and cross-sectional view illustrating a transistor.Top view and cross-sectional view illustrating a transistor.A top view and a cross-sectional view illustrating the method for fabricating a transistor.A diagram illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors, and a diagram showing the limited-field electron diffraction pattern of CAAC-OS.Cross-sectional TEM images of CAAC-OS, as well as planar TEM images and their image analysis results.A figure showing the electron diffraction pattern of nc-OS, and a cross-sectional TEM image of nc-OS.Cross-sectional TEM image of a-like OS.A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation.Cross-sectional view and circuit diagram of a semiconductor device.Cross-sectional view and circuit diagram of a semiconductor device.A plan view showing the imaging device.A plan view showing the pixels of an imaging device.A cross-sectional view showing the imaging device.A cross-sectional view showing the imaging device.A circuit diagram and timing chart illustrating a semiconductor device according to one embodiment of the present invention.Graphs and circuit diagrams illustrating a semiconductor device according to one embodiment of the present invention.A circuit diagram and timing chart illustrating a semiconductor device according to one embodiment of the present invention.A circuit diagram and timing chart illustrating a semiconductor device according to one embodiment of the present invention.A diagram illustrating an example of RF tag configuration.A diagram illustrating an example of a CPU configuration.Circuit diagram of a memory element.A diagram illustrating an example of a display device configuration and a circuit diagram of a pixel.Top view and cross-sectional view of