JP-7856854-B2 - Memory devices and their read operations

Inventors

• シュアン・リウ
• リン・チュ
• マンシ・ワン
• サンシャン・ジアオ

Assignees

• 長江存儲科技有限責任公司

Dates

Publication Date

20260511

Application Date

20230313

Priority Date

20221230

Claims (20)

1. A memory device, A memory cell array and Each of the following is a word line coupled to the row of the memory cell, A peripheral circuit is connected to the array of memory cells through the word line and configured to read a selected row of the memory cells, wherein the peripheral circuit The word line driver comprises a word line driver which is connected to the selected row of the word line through the selected word line of the word line and connected to the unselected row of the memory cell through the unselected word line of the word line, and the word line driver is A pass voltage is applied to the aforementioned unselected word line, The unselected word line is configured to discharge from the pass voltage to a first recovery voltage that is higher than the power supply voltage of the memory cell array. Memory device.
2. The aforementioned word line driver, A reading voltage is applied to the selected word line. The selected word line is further configured to discharge from the reading voltage to a second recovery voltage higher than the power supply voltage. The memory device according to claim 1.
3. The memory device according to claim 2, wherein the second recovery voltage is lower than the first recovery voltage.
4. The memory device according to claim 2 , wherein the non-selected word line is immediately adjacent to the selected word line.
5. The memory device according to claim 4, wherein the word line driver is configured to simultaneously initiate the discharge of the selected word line and the unselected word line.
6. The memory device according to claim 1, further comprising control logic, wherein the peripheral circuit is a control logic coupled to the word line driver and configured to set a duration for the word line driver to discharge the unselected word line.
7. The memory device according to claim 1, further comprising control logic, wherein the peripheral circuit is a control logic coupled to the word line driver and configured to set the first recovery voltage for the word line driver to discharge the unselected word line.
8. The memory device according to claim 1 , wherein the memory device is a three-dimensional (3D) NAND memory device.
9. A method for reading a memory device having memory cells, The steps include applying a pass voltage to an unselected word line coupled to an unselected row of the memory cell, The steps include discharging the unselected word line from the pass voltage to a first recovery voltage higher than the power supply voltage of the memory cell, A method that includes this.
10. The steps include applying a read voltage to the selected word line coupled to the selected row of the memory cell, The steps include: discharging the selected word line from the reading voltage to a second recovery voltage higher than the power supply voltage; The method according to claim 9, further comprising:
11. The method according to claim 10, wherein the second recovery voltage is lower than the first recovery voltage.
12. The method according to claim 10 , wherein the non-selected word line is immediately adjacent to the selected word line.
13. The method according to claim 12, wherein the step of discharging the selected word line and the step of discharging the unselected word line are started simultaneously.
14. The method according to claim 9 , further comprising the step of setting a duration for discharging the non-selected word line.
15. The method according to claim 9 , further comprising the step of setting the first recovery voltage for discharging the unselected word line.
16. The method according to claim 9 , wherein the memory device is a three-dimensional (3D) NAND memory device.
17. A memory device configured to store data, A memory cell array and Each of the following is a word line coupled to the row of the memory cell, A peripheral circuit is connected to the array of memory cells through the word line and configured to read a selected row of the memory cells, wherein the peripheral circuit The word line driver comprises a word line driver which is connected to the selected row of the word line through the selected word line of the word line and connected to the unselected row of the memory cell through the unselected word line of the word line, and the word line driver is A pass voltage is applied to the aforementioned unselected word line, A system comprising a memory device configured to discharge the unselected word line from the pass voltage to a first recovery voltage higher than the power supply voltage of the array of memory cells, and a memory controller coupled to the memory device and configured to control the memory device.
18. The aforementioned word line driver, A reading voltage is applied to the selected word line. The selected word line is further configured to discharge from the reading voltage to a second recovery voltage higher than the power supply voltage. The system according to claim 17.
19. The system according to claim 18, wherein the second recovery voltage is lower than the first recovery voltage.
20. The system according to claim 18 , wherein the non-selected word line is immediately adjacent to the selected word line.

Description

Cross-reference of related applications This application claims the benefit of priority of U.S. Provisional Application No. 63/436,433, filed on 30 December 2022, which is incorporated herein by reference in its entirety. This disclosure relates to a memory device and its operating method. Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations, such as reading, programming (writing), and erasing, can be performed by flash memory. In the case of NAND flash memory, erasing operations can be performed at the block level, while programming or reading operations can be performed at the page level. This is a schematic diagram of a memory device including peripheral circuits according to some aspects of the present disclosure.This is a cross-sectional side view of a memory cell array including a NAND memory string, according to some aspects of the present disclosure.This is a block diagram of a memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure.These are schematic perspective views of a three-dimensional (3D) NAND memory string according to some aspects of the present disclosure.This is a timing diagram for a read operation that includes a recovery phase.This is a timing diagram of a read operation having a shortened recovery phase according to some aspects of the present disclosure.This is a timing diagram for a read operation that includes a recovery phase.This is a timing diagram of a read operation having a shortened recovery phase according to some aspects of the present disclosure.This is a timing diagram of a read operation without a recovery phase, according to some aspects of the present disclosure.This is a flowchart of a method for reading a memory device according to some aspects of the present disclosure.This is a flowchart of another method for reading a memory device according to some aspects of this disclosure.This is a block diagram of a system having a memory device according to some aspects of the present disclosure.This is a diagram of a memory card having a memory device according to some aspects of the present disclosure.This is a diagram of a solid-state drive (SSD) having a memory device according to some aspects of the present disclosure.This figure shows examples of the waveform of the word line voltage applied to the word line during a reading operation, according to some aspects of the present disclosure. This disclosure will be explained with reference to the attached drawings. In general, terms may be understood, at least partially, from their usage within a context. For example, the term “one or more” as used herein may, at least partially depending on the context, be used to express any feature, structure, or characteristic in a singular sense, or to express a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” may, in this case as well, at least partially depending on the context, be understood to convey either a singular or plural use. In addition, the term “based on” may be understood not necessarily to convey an exclusive set of factors; instead, in this case as well, at least partially depending on the context, it may be permitted that the presence of additional factors is not necessarily explicitly expressed. Memory devices such as NAND flash memory can store more than a single bit of information within each memory cell at multiple levels (also called states) to increase storage capacity and reduce the cost per bit. As the storage capacity of each memory cell increases, more distinct states are written within the same threshold voltage window, inevitably worsening the reliability of the stored data. For example, during read operations, charge can move between adjacent word lines, which can cause read interference and impair data retention, thus degrading the reliability of the memory device. To address one or more of the aforementioned problems, this disclosure introduces a solution that shortens and even eliminates the word line discharge/recovery phase at the end of a read operation. From a device reliability standpoint, residual voltage on the word lines after the read phase can be used to reduce and even prevent charge transfer (also known as charge loss) between adjacent word lines, thereby reducing read interference, stabilizing the threshold voltage distribution, and expanding the read window. In the long term, the reduction in charge loss can also improve data retention in memory devices. Furthermore, shortening and even eliminating the recovery phase for read operations can also improve the efficiency of the read operation. Figure 1 shows a schematic circuit diagram of a memory device 100 including peripheral circuits according to several embodiments of this disclosure. The memo