JP-7856869-B1 - Semiconductor equipment

JP7856869B1JP 7856869 B1JP7856869 B1JP 7856869B1JP-7856869-B1

Abstract

A semiconductor device 1 comprises multiple semiconductor chips, multiple inner leads, multiple connectors, and a sealing resin 70. The multiple inner leads include a first common inner lead 20 having a portion extending along a first direction D1 or being arranged along the first direction D1, multiple individual inner leads 31, 32, 33, and a second common inner lead 40. The multiple connectors include first connectors 51, 52, 53 connecting semiconductor chips (diodes 11, 12, 13) mounted on the first common inner lead 20 to the individual inner leads 31, 32, 33, and second connectors 61, 62, 63 connecting semiconductor chips (diodes 14, 15, 16) mounted on the individual inner leads 31, 32, 33 to the second common inner lead 40. Therefore, the semiconductor device 1 of the present invention is a semiconductor device that can suppress the tilting of the inner leads in the sealing resin compared to conventional semiconductor devices.

Inventors

川▲崎▼ 祐生
新井寿和

Assignees

新電元工業株式会社

Dates

Publication Date: 20260511
Application Date: 20250530
Priority Date: 20240718

Claims (8)

A semiconductor device comprising multiple semiconductor chips, multiple inner leads, multiple connectors, and a sealing resin, The aforementioned multiple inner leads are A first common inner lead having a portion extending along a predetermined first direction, A plurality of individual inner leads arranged along the first direction, It includes a second common inner lead that is positioned between the first common inner lead and the plurality of individual inner leads and has a portion that extends along the first direction, At least two of the semiconductor chips are mounted on the first common inner lead in an arrangement that follows the first direction. At least one of the semiconductor chips is mounted on the individual inner lead. The aforementioned plurality of connectors are, A first connector that connects the semiconductor chip mounted on the first common inner lead to the individual inner lead on a one-to-one basis, It includes a second connector that connects the semiconductor chip placed on the individual inner lead and the second common inner lead on a one-to-one basis, The plurality of semiconductor chips include diodes, The plurality of semiconductor chips include six diodes as the diodes, Three of the diodes are mounted on the first common inner lead. The plurality of individual inner leads include three of the individual inner leads, A semiconductor device characterized in that one diode is mounted on the inner lead of the individual piece .
The semiconductor device according to claim 1, characterized in that the plurality of connectors include a number of first connectors equal to the number of semiconductor chips mounted on the first common inner lead, and a number of second connectors equal to the number of semiconductor chips mounted on the plurality of individual inner leads.
When the semiconductor device is viewed from above, the sealing resin has a shape that can define two parallel long sides and two parallel short sides that are perpendicular to the long sides. The semiconductor device according to claim 1 , characterized in that the first direction is parallel to the long side.
The semiconductor device according to claim 3, characterized in that, when the semiconductor device is viewed in plan view, the length of each of the first common inner lead, the plurality of individual inner leads, and the second common inner lead in the direction perpendicular to the first direction is half or less of the length of the sealing resin in the direction perpendicular to the first direction.
The first common inner lead is connected to a first outer lead, one end of which is exposed to the outside of the sealing resin. The individual inner lead is connected to an individual outer lead, one end of which is exposed to the outside of the sealing resin. The semiconductor device according to claim 3 , characterized in that the second common inner lead is connected to a second outer lead, one end of which is exposed to the outside of the sealing resin.
The semiconductor device according to claim 5, characterized in that, when the semiconductor device is viewed in plan view, one end of the first outer lead and one end of the second outer lead are exposed on the side opposite to the side on which one end of the individual outer lead is exposed to the outside of the sealing resin.
The semiconductor device according to claim 6, characterized in that, when the semiconductor device is viewed in plan view, the first outer lead, the second outer lead, and the individual outer leads are arranged symmetrically with respect to one of the individual outer leads.
The semiconductor device according to claim 1, characterized in that, when the semiconductor device is viewed from above, each of the six diodes is covered by either the first connector or the second connector.

Description

Cross-reference This application claims priority under Japanese Patent Application No. 2024-114765, filed in Japan on 18 July 2024, and all contents of said application are incorporated herein by reference. This invention relates to a semiconductor device. Conventionally, semiconductor devices comprising multiple semiconductor chips, multiple inner leads, multiple connectors, and a sealing resin are known (see, for example, Patent Document 1). In such semiconductor devices, it is common for multiple semiconductor chips to be connected together to a single connector. A conventional semiconductor device 900 comprises multiple semiconductor chips 911, 912, 913, 914, 915, and 916, multiple inner leads 921, 922, 923, 924, and 925, multiple connectors 951 and 952, and a sealing resin 970 (see Figure 3). A conventional semiconductor device 900 can also be described as a three-phase bridge diode package. In semiconductor device 900, semiconductor chips 911, 912, and 913 are connected together to connector 951. Also in semiconductor device 900, semiconductor chips 914, 915, and 916 are connected together to connector 952. Japanese Patent Publication No. 2016-149512 This figure shows the internal configuration of the semiconductor device 1 according to Embodiment 1. Figure 1(a) is a plan view, Figure 1(b) is a cross-sectional view taken along A1-A1 in Figure 1(a), and Figure 1(c) is a cross-sectional view taken along A2-A2 in Figure 1(a). In the drawings, "a diagram showing the internal configuration" refers to a diagram showing the components sealed in the sealing resin. For this reason, in Figure 1, only the outer shape of the sealing resin 70 is shown with a dashed line. Also, in Figure 1(a), components hidden by the first connectors 51, 52, 53 and the second connectors 61, 62, 63 are shown with dashed lines.This figure shows the internal configuration of the semiconductor device 2 according to Embodiment 2. Figure 2(a) is a plan view, Figure 2(b) is a cross-sectional view of Figure 2(a) taken along line A3-A3, and Figure 2(c) is a cross-sectional view of Figure 2(a) taken along line A4-A4. In Figure 2, as well, only the outer shape of the sealing resin 70 is shown with a dashed line. Also, in Figure 2(a), components hidden by the first connectors 51, 52 and the second connectors 61, 62 are shown with dashed lines.This is a plan view showing the internal configuration of a conventional semiconductor device 900.This is a cross-sectional view taken along line A-A in Figure 3. Figure 4(a) is a cross-sectional view showing the inner lead 923 in an upright position, while Figures 4(b) and 4(c) are cross-sectional views showing the inner lead 923 in an upright position. Note that in Figures 4(b) and 4(c), the inclination of the inner lead 923 is exaggerated. The semiconductor device of the present invention will be described below based on the embodiments shown in the figures. In the embodiments described below, components having exactly the same or substantially the same function will be referred to by the same reference numerals in each embodiment, even if their shape or other characteristics differ slightly, and explanations that have already been given may be omitted. The embodiments described below do not limit the invention as defined in the claims. Furthermore, not all of the elements and combinations described in each embodiment are necessarily essential to the solution of the present invention. [Embodiment 1] 1. Configuration of the semiconductor device 1 according to Embodiment 1 The semiconductor device 1 according to Embodiment 1 comprises a plurality of semiconductor chips, a plurality of inner leads, a plurality of connectors, and a sealing resin 70 (see Figure 1). The semiconductor device 1 can also be described as a three-phase bridge diode package. The components of the semiconductor device 1 will be described below. The multiple semiconductor chips include diodes. The multiple semiconductor chips include six diodes 11, 12, 13, 14, 15, and 16. Each of the diodes 11, 12, 13, 14, 15, and 16 has electrodes (not shown) on the side facing the inner lead and the side facing the connector. The multiple inner leads include a first common inner lead 20, multiple individual inner leads, and a second common inner lead 40. The inner leads constituting the multiple inner leads are made of conductive metal plates (for example, copper plates). Each inner lead will be described below. The first common inner lead 20 has a portion 20A that extends along a predetermined first direction D1. In the semiconductor device 1, the first direction D1 is parallel to the long side LS (described later) of the sealing resin 70. At least two semiconductor chips are mounted on the first common inner lead 20 in an arrangement that follows the first direction D1. Three diodes 11, 12, and 13 are mounted on the first common inner lead 20. In this specification, "a semiconductor chip is mounted on an inner lead" means that the semiconductor