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JP-7856916-B2 - Electronic devices

JP7856916B2JP 7856916 B2JP7856916 B2JP 7856916B2JP-7856916-B2

Inventors

  • 篠原 規将

Assignees

  • ダイキン工業株式会社

Dates

Publication Date
20260512
Application Date
20240927

Claims (12)

  1. One first memory (11) and A second memory (12) has a slower write speed than the first memory (11) and is non-volatile, An arithmetic unit (13) that can read and write data to the first memory (11) via a bus (15), The system includes a memory control unit (14) that can read data from the first memory (11) and write data to the second memory (12), The data writable capacity of the first memory (11) is greater than or equal to a predetermined capacity. The second memory (12) is configured to allow data to be written and erased in predetermined amounts. The memory control unit (14 ) It has an address boundary to the first memory (11) corresponding to the set capacity, When the address of the first memory (11) to which data is next written from the arithmetic unit (13) exceeds the address boundary, and the amount of data written to the first memory (11) exceeds the set capacity which has an integer multiple of the predetermined capacity, the system is configured to transfer data from the first memory (11) to the second memory (12) . The arithmetic unit (13) is configured to be able to set the address boundary. Electronic devices.
  2. The predetermined capacity is the minimum erase data capacity of the second memory (12), The set capacity has a capacity equal to the predetermined capacity. The electronic device according to claim 1.
  3. The memory control unit (14) is configured to transfer data from the first memory (11) to the second memory (12) regardless of the amount of data written to the first memory (11), based on a signal output from the arithmetic unit (13) or an external terminal (16) that includes a command to transfer data from the first memory (11) to the second memory (12). The electronic device according to claim 1 or 2.
  4. The aforementioned signal is output from the arithmetic unit (13) or the external terminal (16) to the memory control unit (14) based on the interruption of the power supply to the electronic device (10). The electronic device according to claim 3.
  5. The memory control unit (14) is configured to detect the signal from the arithmetic unit (13) or the external terminal (16) by detecting the rising edge or falling edge. The electronic device according to claim 3.
  6. The arithmetic unit (13) is configured to change the settings of the memory control unit (14) via the bus (15). The electronic device according to claim 1 or 2.
  7. The memory control unit (14) is configured to transfer data from the first memory (11) to the second memory (12) without going through the bus (15). The electronic device according to claim 1 or 2.
  8. The memory control unit (14) is configured to perform the erase sequence and write sequence for the second memory (12) itself, without having the arithmetic unit (13) perform them. The electronic device according to claim 7 .
  9. The arithmetic unit (13) is configured to read data written to the second memory (12) via the bus (15). The electronic device according to claim 1 or 2.
  10. The arithmetic unit (13) is configured to check the data to be transferred from the first memory (11) to the second memory (12) by accessing the address of the first memory (11) that is scheduled to be transferred from the first memory (11) to the second memory (12). The electronic device according to claim 1 or 2.
  11. One first memory (11), A second memory (12) has a slower write speed than the first memory (11) and is non-volatile, The system includes an arithmetic unit (21) that can read and write data to the first memory (11) via a bus (15), The data writable capacity of the first memory (11) is greater than or equal to a predetermined capacity. The second memory (12) is configured to allow data to be written and erased in predetermined amounts. The aforementioned computing device (21) It has an address boundary to the first memory (11) corresponding to the set capacity, The system is configured to transfer data from the first memory (11) to the second memory (12) when the address of the first memory (11) to which data is to be written next exceeds the address boundary, and the amount of data written to the first memory (11) exceeds the set capacity which has an integer multiple of the predetermined capacity . The arithmetic unit (21) is configured to be able to set the address boundary. Electronic devices.
  12. The predetermined capacity is the minimum erase data capacity of the second memory (12), The set capacity has a capacity equal to the predetermined capacity. The electronic device according to claim 11 .

Description

This disclosure relates to electronic devices. Patent Document 1 discloses an example of a technique for writing data to non-volatile memory using a microcomputer (hereinafter referred to as "microcontroller"). Japanese Patent Application Publication No. 4-62351 This is a schematic diagram of the outdoor unit for a refrigeration system according to the first embodiment.Figure 1 is a block diagram showing the electrical configuration of the electronic device.This is a conceptual diagram of the bus connecting the arithmetic unit and the first memory.Figure 2 is a flowchart of the process by which the memory control unit, executed by the arithmetic unit, sets the address boundary to the first memory.Figure 2 is a flowchart of the process of transferring data from the first memory to the second memory, which is executed by the memory control unit.This is a block diagram showing the electrical configuration of the electronic device of the second embodiment.Figure 6 is a flowchart of the process of setting the address boundary to the first memory of the arithmetic unit, which is executed by the arithmetic unit.Figure 6 is a flowchart of the process of transferring data from the first memory to the second memory, which is executed by the arithmetic unit.This is a block diagram of the modified electronic device.This is a block diagram of the modified electronic device. <First Embodiment> The electronic device 10 will be described with reference to Figures 1 to 5. Figure 1 shows the outdoor unit 1 for a refrigeration system. In this embodiment, the refrigeration system is an air conditioner. The air conditioner is configured to cool or heat the space within a living room. The air conditioner may be a cooling-only unit, a heating-only unit, or a cooling and heating unit that can switch between cooling and heating. The outdoor unit 1 is connected to the indoor unit of the air conditioner by refrigerant piping. The outdoor unit 1 includes a casing 2. The shape of the casing 2 is not particularly limited. In this embodiment, the casing 2 is, for example, a horizontally elongated rectangular parallelepiped. The outdoor unit 1 comprises a fan 3 and an electrical component housing 4. The fan 3 and the electrical component housing 4 are housed in a casing 2. The electrical component housing 4 contains a power supply circuit, a printed circuit board 5 on which electronic devices 10, etc., are mounted, and wiring electrically connected to the printed circuit board 5. <Electronic Devices> The electronic device 10 is a microcontroller. The microcontroller in this embodiment is a semiconductor chip configured to control the electrical circuits and mechanical parts of the outdoor unit 1. As shown in Figures 2 and 3, the electronic device 10 comprises a first memory 11, a second memory 12, an arithmetic unit 13, and a memory control unit 14. The first memory 11 has a high write speed and is volatile. The first memory 11 is directly accessible from the arithmetic unit 13 and the memory control unit 14. The first memory 11 includes, for example, RAM (Random Access Memory). In this embodiment, the first memory 11 includes SRAM (Static Random Access Memory). The first memory 11 may also include DRAM (Dynamic Random Access Memory). Information regarding the interruption of power supply to the outdoor unit 1 and information necessary for the maintenance of the outdoor unit 1 are written to the first memory 11 from the arithmetic unit 13. The first memory 11 has a data capacity of at least twice the minimum erase data capacity of the second memory 12, described later. The first memory 11 has, for example, a first surface and a second surface. Each of the first and second surfaces of the first memory 11 has a physical storage medium. The two physical storage media are integrated as a single memory area. The data capacity that can be stored on each of the first and second surfaces is equal. Each of the first and second surfaces has a data capacity equal to its set capacity. Each of the first and second surfaces has a data capacity equal to the minimum erase data capacity of the second memory 12. Data written from the arithmetic unit 13 to the first memory 11 is written alternately to the first and second surfaces. If data has already been written to the first and second surfaces, it is overwritten. The second memory 12 has a slower write speed than the first memory 11 and is non-volatile. The second memory 12 is directly accessible from the arithmetic unit 13 and the memory control unit 14. The second memory 12 includes flash memory. The flash memory in this embodiment is a NOR type flash memory. The second memory 12 may also include EEPROM (Electrically Erasable Programmable Read-Only Memory). The second memory 12 has multiple blocks that equally partition the data area of the second memory 12. Each block is assigned an address. Each block has the same data capacity. The data capacity of each block corresponds to the minimum erase data ca