JP-7857118-B2 - differential amplifier

JP7857118B2JP 7857118 B2JP7857118 B2JP 7857118B2JP-7857118-B2

Inventors

小川正訓
森下伊織

Assignees

日清紡マイクロデバイス株式会社

Dates

Publication Date: 20260512
Application Date: 20220307

Claims (15)

In a differential amplifier in which a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs are provided in parallel with respect to the input, and the outputs of each are configured to be summable, A current mirror circuit is provided, and the current mirror circuit is The output stage of the first differential pair and the output stage of the second differential pair are configured to be able to supply current to each of them, This makes it possible to suppress voltage fluctuations in the output stages of the first and second differential pairs due to the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage. A tail current supply circuit is provided to supply the tail current of the first differential pair. The current mirror circuit comprises an input stage transistor using a P-channel MOSFET and first to fourth output stage transistors. The sources of the input stage transistor and the sources of the first to fourth output stage transistors are interconnected to allow a positive power supply voltage to be applied. The gates of the input stage transistor and the gates of the first to fourth output stage transistors are interconnected and connected to the drains of the input stage transistors. The drains of the input stage transistors are connected to the output stage of the tail current supply circuit. A differential amplifier characterized in that the drains of the first and second output stage transistors are connected to the two output stages of the second differential pair, and the drains of the third and fourth output stage transistors are connected to the two output stages of the first differential pair.
Between the drain of the input stage transistor and the output stage of the tail current supply circuit, a cascode input stage transistor using a P-channel MOSFET is provided. The source of the cascode input stage transistor is connected to the drain of the input stage transistor, and the drain of the cascode input stage transistor, along with its gate, is connected to the output stage of the tail current supply circuit. A first cascode output stage transistor is provided between the drain of the first output stage transistor and one of the output stages of the second differential pair. The source of the first cascode output stage transistor is connected to the drain of the first output stage transistor, the gate of the first cascode output stage transistor is connected to the gate of the cascode input stage transistor, and the drain of the first cascode output stage transistor is connected to one of the output stages of the second differential pair. The differential amplifier according to claim 1, characterized in that a second cascode output stage transistor is provided between the drain of the second output stage transistor and the other output stage of the second differential pair, the source of the second cascode output stage transistor is connected to the drain of the second output stage transistor, the gate of the second cascode output stage transistor is connected to the gate of the cascode input stage transistor, and the drain of the second cascode output stage transistor is connected to the other output stage of the second differential pair.
The first differential pair is configured such that the gate of the first transistor for the first differential pair is connected to the inverting input terminal, and the gate of the second transistor for the first differential pair is connected to the non-inverting input terminal. The positive power supply voltage is applied to the drain of the first transistor for the first differential pair via a first resistor, and to the drain of the second transistor for the first differential pair via a second resistor. The differential amplifier according to claim 1 or 2, characterized in that the overdrive voltage of the fourth output stage transistor connected to the drain of the first differential pair first transistor is equal to the overdrive voltage of the third output stage transistor connected to the drain of the first differential pair second transistor, and is set to be less than or equal to the voltage drop across the second resistor.
In a differential amplifier in which a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs are provided in parallel with respect to the input, and the outputs of each are configured to be summable, A first current mirror circuit and a second current mirror circuit are provided. The first current mirror circuit is configured to supply current to the output stage of the second differential pair, The second current mirror circuit is configured to supply current to the output stage of the first differential pair, This makes it possible to suppress voltage fluctuations in the output stages of the first and second differential pairs due to the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage. The first and second current mirror circuits described above are made using P-channel MOSFETs. The first current mirror circuit comprises a first current mirror input stage transistor and first and second output stage transistors for the first current mirror. The second current mirror circuit comprises a second current mirror input stage transistor and first and second output stage transistors for the second current mirror. In the first current mirror circuit, the source of the first current mirror input stage transistor and the sources of the first and second output stage transistors for the first current mirror are interconnected so that a positive power supply voltage can be applied. The gate of the first current mirror input stage transistor and the gates of the first and second output stage transistors for the first current mirror are interconnected and connected to the drain of the first current mirror input stage transistor, and the drain of the first current mirror input stage transistor is connected to the output stage of the tail current supply circuit . The drains of the first and second output stage transistors for the first current mirror are connected to the two output stages of the second differential pair, respectively. In the second current mirror circuit, the source of the input stage transistor for the second current mirror and the sources of the first and second output transistors for the second current mirror are interconnected so that a positive power supply voltage can be applied. The gate of the input stage transistor for the second current mirror and the gates of the first and second output stage transistors for the second current mirror are interconnected and connected to the drain of the input stage transistor for the second current mirror, and the drain of the input stage transistor for the second current mirror is connected to the output stage of the tail current supply circuit . A differential amplifier characterized in that the drains of the first and second output stage transistors for the second current mirror are connected to the two output stages of the first differential pair, respectively.
The differential amplifier according to claim 4, characterized in that the source of the first current mirror input stage transistor is connected via a first adjustment resistor, the source of the first current mirror first output stage transistor is connected via a second adjustment resistor, and the source of the first current mirror second output stage transistor is connected via a third adjustment resistor, all of which are connected to the positive power supply voltage.
The differential amplifier according to claim 5 , characterized in that the second and third adjustment resistors are variable resistors configured to have variable resistance values.
In a differential amplifier in which a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs are provided in parallel with respect to the input, and the outputs of each are configured to be summable, An offset adjustment circuit and a second current mirror circuit are provided. The offset adjustment circuit is configured to supply current to the output stage of the second differential pair, The second current mirror circuit is configured to supply current to the output stage of the first differential pair, This makes it possible to suppress voltage fluctuations in the output stages of the first and second differential pairs due to the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage. The offset adjustment circuit comprises first and second transistors for the offset adjustment circuit, each using a P-channel MOSFET. The gates of the first and second transistors for the offset adjustment circuit are connected to each other so that an external reference voltage can be applied. The sources of the first and second transistors for the offset adjustment circuit are connected to the first constant current source, which is the current source for the second differential pair, The drain of the first transistor for the offset adjustment circuit is connected to one output stage of the second differential pair, and the drain of the second transistor for the offset adjustment circuit is connected to the other output stage of the second differential pair. In the second current mirror circuit, the source of the input stage transistor for the second current mirror and the sources of the first and second output transistors for the second current mirror are interconnected so that a positive power supply voltage can be applied. The gate of the input stage transistor for the second current mirror and the gates of the first and second output stage transistors for the second current mirror are interconnected and connected to the drain of the input stage transistor for the second current mirror, and the drain of the input stage transistor for the second current mirror is connected to the output stage of the tail current supply circuit. A differential amplifier characterized in that the drains of the first and second output stage transistors for the second current mirror are connected to the two output stages of the first differential pair, respectively .
The first differential pair is configured such that the gate of the first transistor for the first differential pair is connected to the inverting input terminal, and the gate of the second transistor for the first differential pair is connected to the non-inverting input terminal. The positive power supply voltage is applied to the drain of the first transistor for the first differential pair via a first resistor, and to the drain of the second transistor for the first differential pair via a second resistor. A differential amplifier according to any one of claims 4 to 7, characterized in that the overdrive voltage of the second output stage transistor for the second current mirror, which is connected to the drain of the first differential pair transistor, is equal to the overdrive voltage of the first output stage transistor for the second current mirror , which is connected to the drain of the first differential pair transistor, and is set to be less than or equal to the voltage drop across the second resistor.
In a differential amplifier in which a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs are provided in parallel with respect to the input, and the outputs of each are configured to be summable, A first current mirror circuit is provided. The first current mirror circuit is configured to supply current to the output stage of the second differential pair, A differential amplifier characterized by its ability to suppress voltage fluctuations in the output stages of the first and second differential pairs caused by the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage .
The first current mirror circuit comprises a first current mirror input stage transistor using a P-channel MOSFET, and first and second output stage transistors for the first current mirror. The source of the first current mirror input stage transistor and the sources of the first and second output stage transistors for the first current mirror are interconnected so that the positive power supply voltage can be applied. The gate of the first current mirror input stage transistor and the gates of the first and second output stage transistors for the first current mirror are interconnected and connected to the drain of the first current mirror input stage transistor, and the drain of the first current mirror input stage transistor is connected to the output stage of the tail current supply circuit . The differential amplifier according to claim 9 , characterized in that the drains of the first and second output stage transistors for the first current mirror are connected to the two output stages of the second differential pair, respectively.
The differential amplifier according to claim 10, characterized in that the source of the first current mirror input stage transistor is connected to a first adjustable resistor, the source of the first current mirror first output stage transistor is connected to a second adjustable resistor, and the source of the first current mirror second output stage transistor is connected to a third adjustable resistor, all of which are connected to the positive power supply voltage.
The differential amplifier according to claim 11 , characterized in that the second and third adjustment resistors are variable resistors configured to have variable resistance values.
In a differential amplifier in which a first differential pair configured to be differentially amplified using N-channel MOSFETs and a second differential pair configured to be differentially amplified using P-channel MOSFETs are provided in parallel with respect to the input, and the outputs of each are configured to be summable, A second offset adjustment circuit is provided. The second offset adjustment circuit is configured to supply current to the output stages of the first and second differential pairs, respectively. This makes it possible to suppress voltage fluctuations in the output stages of the first and second differential pairs due to the switching of operation between the first and second differential pairs in response to changes in the common-mode input voltage. The second offset adjustment circuit comprises first to fourth transistors for the offset adjustment circuit, each using a P-channel MOSFET. The gates of the first to fourth transistors for the offset adjustment circuit are interconnected so that an external reference voltage can be applied to them. The sources of the first to fourth transistors for the offset adjustment circuit are connected to the first constant current source, which is the current source for the second differential pair, The drain of the first transistor for the offset adjustment circuit is connected to one of the output stages of the second differential pair. The drain of the second transistor for the offset adjustment circuit is connected to the output stage of the other side of the second differential pair. The drain of the third transistor for the offset adjustment circuit is connected to one of the output stages of the first differential pair. A differential amplifier characterized in that the drains of the fourth transistors for the offset adjustment circuit are connected to the other output stage of the first differential pair.
The first differential pair is configured such that the gate of the first transistor for the first differential pair is connected to the inverting input terminal, and the gate of the second transistor for the first differential pair is connected to the non-inverting input terminal. The positive power supply voltage is applied to the drain of the first transistor for the first differential pair via a first resistor, and to the drain of the second transistor for the first differential pair via a second resistor. The differential amplifier according to claim 13, characterized in that the value obtained by adding the reference voltage to the absolute value of the threshold voltage of the third transistor for the offset adjustment circuit connected to the drain of the first differential pair first transistor is equal to the value obtained by adding the reference voltage to the absolute value of the threshold voltage of the fourth transistor for the offset adjustment circuit connected to the drain of the second transistor for the first differential pair, and is set to be greater than the value obtained by subtracting the voltage drop across the second resistor from the positive power supply voltage.
A differential amplifier according to any one of claims 1, 2, 4 to 7, or 9 to 13, characterized in that it uses bipolar elements instead of CMOS elements.

Description

This invention relates to a differential amplifier used in operational amplifiers and comparators, and more particularly to one that improves the input offset voltage with respect to the common-mode input voltage. Operational amplifiers and comparators are ideally designed to have a wide common-mode input voltage range and minimal variation in the input offset voltage relative to the common-mode input voltage. Figure 18 shows a circuit diagram of a conventional operational amplifier using a differential amplifier capable of applying a common-mode input voltage from the negative power supply voltage to the positive power supply voltage. The following description of this conventional operational amplifier will be made with reference to this figure. This conventional operational amplifier is broadly composed of a first differential pair 101X made up of first and second transistors M1 and M2, a second differential pair 102X made up of third and fourth transistors M3 and M4 and a first constant current source CS1, a folded cascode circuit 103X made up of fifth to eighth transistors M5 to M8, and a tail current supply circuit 104X made up of tenth to twelfth transistors M10 to M12. Figure 19 shows the common-mode input voltage characteristics of the input offset voltage in this conventional operational amplifier. The operation of this operational amplifier will be outlined with reference to this figure. This common-mode input voltage characteristic plots the input offset voltage when the common-mode input voltage Vicm is swept from 0V to 5V, with a positive power supply voltage VDD = 5V and a negative power supply voltage VSS = 0V. As shown in Figure 19, it can be confirmed that the conventional operational amplifier switches between PMOS differential pair operation and NMOS differential pair operation at a common-mode input voltage Vicm = 3.5V. Here, the PMOS differential pair refers to the second differential pair 102X in Figure 18, and the NMOS differential pair refers to the first differential pair 101X in Figure 18. The reason why the operation switches between PMOS differential pair operation and NMOS differential pair operation at a common-mode input voltage Vicm = 3.5V is because a reference voltage Vref1 = 3.5V is supplied to the reference voltage terminal 45X in Figure 18. The operation switches between PMOS differential pair operation and NMOS differential pair operation at the voltage supplied to this reference voltage terminal 45X. Therefore, the circuit operation switches as described below, with the common-mode input voltage Vicm = 3.5V as the boundary. First, when the common-mode input voltage Vicm is between the negative power supply voltage VSS and the reference voltage Vref1, the PMOS differential pair operates while the NMOS differential pair remains inactive. Furthermore, when the common-mode input voltage Vicm is between the reference voltage Vref1 and the positive power supply voltage VDD, the PMOS differential pair is in a non-operating state, while the NMOS differential pair is in an operating state. Thus, in conventional operational amplifiers, because switching of the operating differential pair occurs, as shown in Figure 19, when the common-mode input voltage Vicm = 3.5V or less, the input offset voltage is approximately 0mV, but when the common-mode input voltage Vicm = 3.5V or higher, the input offset voltage deteriorates to 0.4mV or more. The reason why the input offset voltage deteriorates during NMOS differential pair operation is explained below. To state the conclusion first, the reason for the deterioration of the input offset voltage is that the magnitude of the voltage drop across resistor R4 changes between PMOS differential pair operation and NMOS differential pair operation. This matter will be explained in detail below. First, we derive the voltage drop across resistor R4 during PMOS differential pair operation. To determine the voltage drop across resistor R4, we derive the drain current IM6 of transistor M6 during PMOS differential pair operation. This current IM6 is determined using the constant current source CS2, transistors M6 and M9, and resistors R2 and R5 so as to satisfy the relationship shown in Equation 1 below. (IM6×R2)+[2×IM6/{k'P×(W/L)M6}] 1/2 = (IM9×R5)+[2×IM9/{k'P×(W/L)M9}] 1/2 ...Formula 1 Here, IM6 is the drain current of transistor M6, R2 is the resistance value of resistor R2, k'P is the product of the PMOS transistor's mobility and gate oxide capacitance per unit area, (W/L)M6 is the value obtained by dividing the channel width W of transistor M6 by the channel length L, IM9 is the drain current of transistor M9, R5 is the resistance value of resistor R5, and (W/L)M9 is the value obtained by dividing the channel width W of transistor M9 by the channel length L. In Equation 1, if R2 = R5 and (W/L)M6 = (W/L)M9, then the drain current IM6 of transistor M6 is the same magnitude as the drain current IM9 of transistor M9. Furthermore, the drain current IM9