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JP-7857169-B2 - Method for forming conductive patterns

JP7857169B2JP 7857169 B2JP7857169 B2JP 7857169B2JP-7857169-B2

Inventors

  • 豊島 良一

Assignees

  • メクテック株式会社

Dates

Publication Date
20260512
Application Date
20220615

Claims (9)

  1. A method for forming a conductive pattern by a semi-additive method, A step of preparing an insulating substrate having a seed layer on its main surface, and forming a resist layer on the seed layer, The steps include forming an opening for a conductive pattern and an opening for a dummy pattern in the resist layer, A step of forming a plating layer on the seed layer exposed in the openings for the conductive pattern and the openings for the dummy pattern by electroplating, The step of removing the resist layer, A step of removing an exposed seed layer that is not covered by the plating layer from the seed layer by etching, wherein the plating layer formed in the dummy pattern opening is removed together with the exposed seed layer. Equipped with , A method for forming the conductive pattern opening and the dummy pattern opening, wherein the dummy pattern opening is formed such that its opening width narrows at its bottom .
  2. The steps of forming the conductive pattern opening and the dummy pattern opening are as follows: A step of exposing the resist layer such that the size of the dummy pattern opening is less than or equal to the lower limit of the achievable opening size based on the material of the resist layer and the performance of the exposure apparatus, The method according to claim 1 , comprising the step of developing the exposed resist layer to form the opening for the conductive pattern and the opening for the dummy pattern.
  3. When the resist layer is negative type, the step of forming the opening for the conductive pattern and the opening for the dummy pattern is: A step of exposing the resist layer such that the amount of exposure around the area where the dummy pattern opening is to be formed is greater than the amount of exposure to other areas, The method according to claim 1 , comprising the step of developing the exposed resist layer to form the opening for the conductive pattern and the opening for the dummy pattern.
  4. The method according to claim 3 , wherein the exposure amount to the area surrounding the region where the dummy pattern opening is to be formed is 1.5 times or more the exposure amount to the other regions.
  5. When the resist layer is of the positive type, the steps of forming the opening for the conductive pattern and the opening for the dummy pattern are as follows: A step of exposing the resist layer such that the amount of exposure to the area where the dummy pattern opening is to be formed is less than the amount of exposure to other areas, The method according to claim 1 , comprising the step of developing the exposed resist layer to form the opening for the conductive pattern and the opening for the dummy pattern.
  6. The method according to any one of claims 1 to 5, wherein the width of the dummy pattern opening is smaller than the width of the conductive pattern opening, and in the step of removing the exposed seed layer by etching, an etchant that preferentially etches the interface between the seed layer and the plating layer is used.
  7. A method for forming a conductive pattern by a semi-additive method, A step of preparing an insulating substrate having a seed layer on its main surface, and forming a resist layer on the seed layer, The steps include forming an opening for a conductive pattern and an opening for a dummy pattern in the resist layer, A step of forming a plating layer on the seed layer exposed in the openings for the conductive pattern and the openings for the dummy pattern by electroplating, The step of removing the resist layer, A step of removing an exposed seed layer that is not covered by the plating layer from the seed layer by etching, wherein the plating layer formed in the dummy pattern opening is removed together with the exposed seed layer. Equipped with, The method wherein the shape of the opening for the dummy pattern is circular, a regular polygon, or a star shape.
  8. The method according to claim 1, wherein the insulating substrate is flexible, and the dummy pattern opening is formed in the region where the insulating substrate is bent, the region where high-speed signal lines are formed, and/or the region where the outer shape is processed.
  9. A method comprising performing at least one of the steps described in claim 1 using a roll-to-roll method.

Description

This invention relates to a method for forming conductive patterns, and more specifically, to a method for forming conductive patterns on an insulating substrate by a semi-additive method. Conventionally, the semi-additive method is known as one method for forming conductive patterns on insulating substrates. The semi-additive method involves preparing a substrate with a thin conductive layer called a seed layer on top of the insulating substrate, and then performing electroplating on the openings of a plating resist formed on top of it. This technique forms conductive patterns such as wiring, pads, and grounds on the seed layer exposed at the openings. During the electroplating process, current is applied from any position on the substrate through the seed layer, causing the plating to deposit from the openings in the plating resist. In the semi-additive method, the shape of the openings in the plating resist almost directly corresponds to the shape of the conductive pattern, making it advantageous for forming fine wiring compared to the subtractive method. Furthermore, Patent Document 1 describes a pattern plating method aimed at obtaining a wiring pattern with a uniform film thickness in a pattern plating area where one or more block wiring patterns with different pattern densities exist. Japanese Patent Publication No. 2004-263218 This is a flowchart illustrating the conductive pattern formation method according to the first embodiment.This is a cross-sectional view illustrating a conductive pattern formation method according to the first embodiment.This is a cross-sectional view of the process for explaining the conductive pattern formation method according to the first embodiment, following Figure 2A.(a), (b), and (c) are all plan views showing examples of dummy pattern shapes.This is an SEM image showing an example of a cross-section of a dummy pattern during etching according to the first embodiment.This is a flowchart illustrating the conductive pattern formation method according to the second embodiment.This is a cross-sectional view illustrating a conductive pattern formation method according to a second embodiment.This is a cross-sectional view illustrating the conductive pattern formation method according to the second embodiment, following Figure 6A.This is an SEM image showing an example of a cross-section of a dummy pattern during etching according to the second embodiment.Both (a) and (b) are plan views of a flexible printed circuit board to illustrate examples where dummy patterns cannot be left in place. The embodiments of the present invention will be described below with reference to the drawings. Note that the drawings are schematic and primarily show characteristic parts of each embodiment; the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality. (First embodiment) The conductive pattern formation method according to the first embodiment will be described with reference to the flowchart in Figure 1 and the process cross-sectional views in Figures 2A and 2B. This embodiment is a method for forming a conductive pattern on an insulating substrate having a conductive layer formation region and a conductive layer formation prohibited region by a semi-additive method. As shown in Figure 2A(1), an insulating substrate 11 is prepared with a seed layer 12 provided on its main surface (step S11). In this embodiment, the insulating substrate 11 is made of a flexible material such as polyimide. The seed layer 12 is, for example, a copper seed layer with a thickness of 2 μm. Furthermore, the material of the insulating substrate 11 is not limited to polyimide-based materials; for example, it may be a liquid crystal polymer (LCP), a fluorine-based material (PFA, PTFE, etc.). Next, as shown in Figure 2A(2), a resist layer (plating resist) 13 is formed on the seed layer 12 (step S12). The resist layer 13 is made of a photosensitive material. In this embodiment, the resist layer 13 is negative type. Next, as shown in Figure 2A(3), conductive pattern openings 13p and dummy pattern openings 13d are formed in the resist layer 13 (step S13). In this step, the dummy pattern openings 13d are formed in the region where the insulating substrate 11 is bent in the use or mounting state, the region where high-speed signal lines are formed, and/or the region where external shaping is performed. The region where external shaping is performed is the region where punching or similar processes are performed, and it is a region where metal such as a plating layer is not to be placed. The dummy pattern openings 13d are formed so that the density of openings in the resist layer 13 (conductive pattern openings 13p and dummy pattern openings 13d) is approximately uniform. For example, the width of the conductive pattern opening 13p is 20 μm, and the width of the dummy pattern opening 13d is 10 μm. Step S13 is performed by a photolithography process.