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JP-7857383-B2 - display device

JP7857383B2JP 7857383 B2JP7857383 B2JP 7857383B2JP-7857383-B2

Inventors

  • パク スビン
  • ホ ジュン
  • キム キョンソク
  • ユ スンウク
  • パク ラクヘ

Assignees

  • エルジー ディスプレイ カンパニー リミテッド

Dates

Publication Date
20260512
Application Date
20241212
Priority Date
20240227

Claims (17)

  1. A display panel including multiple data lines and pixels connected to the data lines, A first data drive unit including a plurality of first data ICs connected to one end of the plurality of data wirings, A second data drive unit including a plurality of second data ICs connected to the other ends of the plurality of data wirings, A timing control unit that provides an input first lock signal to the first data drive unit and an input second lock signal to the second data drive unit, The system includes a comparison circuit that directly receives an output first lock signal generated based on the input first lock signal from the first data drive unit, directly receives an output second lock signal generated based on the input second lock signal from the second data drive unit, compares the output first lock signal and the output second lock signal, and provides a synchronous lock signal generated by synchronizing the lock state based on the output first lock signal and the output second lock signal to the timing control unit. The timing control unit transmits video data to the first data drive unit and the second data drive unit while the synchronization lock signal is locked, and the first data drive unit and the second data drive unit output data voltages . During the interval in which the lock states of the first output lock signal and the second output lock signal are asynchronous, or during the interval in which at least one of the first output lock signal and the second output lock signal is in a lock failure state, the power supply unit supplies the source drive voltage to the first data drive unit and the second data drive unit. Display device.
  2. During the interval in which the lock states of the first output lock signal and the second output lock signal are asynchronous, the synchronous lock signal has an unlocked state. When the synchronization lock signal is unlocked, the timing control unit turns off the transmission of the video data, and the outputs of the first data drive unit and the second data drive unit are turned off. The display device according to claim 1.
  3. During the interval in which at least one of the output first lock signal and the output second lock signal is in the lock failure state, the synchronization lock signal is in the unlock state. When the synchronization lock signal is unlocked, the timing control unit turns off the transmission of the video data, and the outputs of the first data drive unit and the second data drive unit are turned off. The display device according to claim 1.
  4. The display device according to claim 2, wherein, in the interval where the lock states of the first output lock signal and the second output lock signal are asynchronous, one of the first output lock signal and the other of the second output lock signal is in a locked state and the other is in an unlocked state.
  5. The display device according to claim 3, wherein at least one of the output first lock signal and the output second lock signal has an abnormal waveform in the lock failure state.
  6. When the input first lock signal is received, the plurality of first data ICs operate sequentially and output lock signals. The lock signal output from the first data IC is input to the next first data IC, and the lock signal output from the last first data IC is the output first lock signal. When the input second lock signal is received, the plurality of second data ICs operate sequentially and output lock signals. The lock signal output from one second data IC is input to the next second data IC, and the lock signal output from the last second data IC is the output second lock signal. The display device according to claim 1.
  7. The first data drive unit includes a first source board to which the plurality of first data ICs are connected. The second data drive unit includes a second source board to which the plurality of second data ICs are connected. The first source board includes a first lock signal wiring that transmits input and output lock signals to the plurality of first data ICs, The second source board includes a second lock signal wiring that transmits input and output lock signals to the plurality of second data ICs. The display device according to claim 6.
  8. The display device according to claim 1, wherein the pixel includes a light-emitting diode.
  9. The display device according to claim 1, wherein, in the locked state of the synchronization lock signal, the outputs of the data voltages of the first data drive unit and the second data drive unit are synchronized.
  10. A display panel including multiple data lines and pixels connected to the data lines, A first data drive unit including a plurality of first data ICs connected to one end of the plurality of data wirings, A second data drive unit including a plurality of second data ICs connected to the other ends of the plurality of data wirings, A timing control unit that provides an input first lock signal to the first data drive unit and an input second lock signal to the second data drive unit, The system includes a comparison circuit that directly receives an output first lock signal generated based on the input first lock signal from the first data drive unit, directly receives an output second lock signal generated based on the input second lock signal from the second data drive unit, compares the output first lock signal and the output second lock signal, and provides a synchronous lock signal generated by synchronizing the lock state based on the output first lock signal and the output second lock signal to the timing control unit. In the locked state of the synchronization lock signal, the outputs of the data voltages of the first data drive unit and the second data drive unit are synchronized. During the interval in which the lock states of the first output lock signal and the second output lock signal are asynchronous, or during the interval in which at least one of the first output lock signal and the second output lock signal is in a lock failure state, the power supply unit supplies the source drive voltage to the first data drive unit and the second data drive unit. Display device.
  11. During the interval in which the lock states of the first output lock signal and the second output lock signal become asynchronous with respect to each other, the synchronous lock signal has an unlocked state. When the synchronization lock signal is unlocked, the outputs of the first data drive unit and the second data drive unit are turned off. The display device according to claim 10.
  12. During the interval in which at least one of the output first lock signal and the output second lock signal is in the lock failure state, the synchronization lock signal has an unlock state. When the synchronization lock signal is unlocked, the outputs of the first data drive unit and the second data drive unit are turned off. The display device according to claim 10.
  13. The display device according to claim 11, wherein, in the interval where the lock states of the first output lock signal and the second output lock signal are asynchronous, one of the first output lock signal and the other of the second output lock signal is in a locked state and the other is in an unlocked state.
  14. The display device according to claim 12, wherein at least one of the output first lock signal and the output second lock signal has an abnormal waveform in the lock failure state.
  15. The first data drive unit includes a first source board to which the plurality of first data ICs are connected. The second data drive unit includes a second source board to which the plurality of second data ICs are connected. The first source board includes a first lock signal wiring that transmits input and output lock signals to the plurality of first data ICs, The second source board includes a second lock signal wiring that transmits input and output lock signals to the plurality of second data ICs. The display device according to claim 10.
  16. The display device according to claim 10, wherein the pixel includes a light-emitting diode.
  17. The display device according to claim 10, wherein the data voltages output from the first data drive unit and the second data drive unit are identical to each other.

Description

This invention relates to a display device. As the information society progresses, various demands for display devices for displaying images are increasing, and recently, various flat-panel displays such as organic light-emitting displays and liquid crystal displays are being utilized. In recent years, organic light-emitting display devices have been driven using a double-bank structure, where data drive units are located at both ends of the data wiring. In this double-bank structure, the same lock signal is simultaneously input to both the preceding and succeeding data drive units. In response, each of these units generates and outputs an output lock signal. However, due to differences in electrical characteristics between the preceding and succeeding data drive units, the timing of the output lock signal may not match, resulting in asynchronous operation. In this case, the output timing of the preceding and succeeding data drive units does not coincide, resulting in asynchronous operation. This creates a potential difference in data voltage between the upper and lower ends of the channel, potentially causing overcurrent. Furthermore, this overcurrent could lead to overheating or even burning of the data IC. This figure schematically shows a display device according to an embodiment of the present invention.This is a schematic circuit diagram showing an example of a pixel according to an embodiment of the present invention.This figure schematically shows the configuration of the gate drive unit of a display device according to an embodiment of the present invention.This timing diagram schematically shows an example of a drive signal output from a gate drive unit according to an embodiment of the present invention.This is a schematic cross-sectional view showing an example of the cross-sectional structure of a display panel according to an embodiment of the present invention.This figure schematically shows the timing control unit, data drive unit, and comparison circuit of a display device according to an embodiment of the present invention.This timing diagram schematically shows the input lock signal, output lock signal, synchronization lock signal, and data voltage output according to an embodiment of the present invention.In an embodiment of the present invention, this timing diagram schematically shows examples of input lock signals, output lock signals, synchronous lock signals, and data voltage outputs in the event of asynchronous operation and lock failure of the output lock signal.In a comparative example of the present invention, the timing diagram schematically shows examples of the input lock signal, output lock signal, and data voltage output when asynchronous output lock signal and lock failure occur. The advantages and features of the present invention, and methods for achieving them, will become clearer with reference to the embodiments detailed with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in various different forms. These embodiments are provided to ensure that the disclosure of the present invention is complete and that a person ordinary skill in the art to which the invention pertains fully understands the scope of the invention, and the present invention is defined by the scope of the claims. The shapes, sizes, proportions, angles, and quantities disclosed in the drawings illustrating embodiments of the present invention are illustrative and the present invention is not limited thereto. Throughout the specification, the same reference numerals indicate the same components. Furthermore, in describing the present invention, if a specific explanation of related prior art is deemed to obscure the gist of the invention, such detailed explanation will be omitted. Where "equipped with," "includes," "possesses," "has," "becomes," etc., are used in this specification, other parts may be added unless "only/only" is also used. Also, where a component is described in the singular form, it may be interpreted as plural unless explicitly stated otherwise. Furthermore, when interpreting the constituent elements, a margin of error shall be included even if not explicitly stated. For example, when describing the positional relationship between two components using terms like "adjacent" or "nearby," if the terms "direct" or "directly" are not used, one or more other components may be located between those two components. Furthermore, when describing temporal relationships using phrases such as "after," "following," "next," or "before," discontinuous cases can be included unless "immediately" or "soon" is explicitly stated. Also, while terms such as "first" and "second" are used to distinguish components, the components are not limited to these terms. Therefore, the first component mentioned below may also be the second component within the technical concept of this invention. The features of each of the multiple embodiments of the pr