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JP-7857412-B2 - Fiber array, optical integrated circuit, and method for manufacturing an optical integrated circuit

JP7857412B2JP 7857412 B2JP7857412 B2JP 7857412B2JP-7857412-B2

Inventors

  • シエ ウー
  • ルオ シャンシュー
  • ロー グオ-チアン

Assignees

  • アドバンスド マイクロ ファウンドリー ピーティーイー.リミテッド

Dates

Publication Date
20260512
Application Date
20220228

Claims (12)

  1. A fiber array for edge coupling at the edge of a fiber array, comprising at least one optical fiber and at least one wafer substrate, Optical fiber core and A fiber cladding having an edge, top, and bottom, covering the optical fiber core, The V-groove mount on the upper part of the fiber cladding, The fiber cladding comprises a fiber array lid at the bottom of the fiber cladding, The fiber cladding and the V-groove mount have a uniform cross-section perpendicular to the optical axis of the optical fiber at their edges, and the fiber array lid has a taper at its edges. Fiber array.
  2. The fiber array according to claim 1, wherein the optical fiber core is single-mode, and the optical fiber core has a uniform cross-section perpendicular to the optical axis of the optical fiber at the edge of the fiber cladding .
  3. The fiber array according to claim 1, wherein the fiber array lid is made of a polymer.
  4. The fiber array according to claim 1, wherein the taper angle of the fiber array lid is 30° to 45°.
  5. Wafer substrate and A fiber array according to claim 1, coupled in-plane to the wafer substrate, Equipped with, Optical integrated circuit.
  6. The optical integrated circuit according to claim 5, wherein the optical fiber core is single-mode.
  7. The optical integrated circuit according to claim 5, wherein the optical fiber core is multimode.
  8. The optical integrated circuit according to claim 5, wherein the taper angle of the polished fiber array lid is 30° to 45°.
  9. The wafer substrate includes a deep trench structure, The fiber array is aligned on the deep trench structure, The alignment includes the angle and position of the fiber array lid, The angle of the fiber array lid is determined by the depth of the deep trench structure. The optical integrated circuit according to claim 5.
  10. A method for manufacturing an optical integrated circuit according to claim 9 , a) The step of etching the silicon substrate of the wafer substrate to form a deep trench structure so that the deep trench structure forms an optical interface for edge coupling, b) A step of performing a first polishing of the fiber array lid to form a polished fiber array lid aligned with the wafer substrate above the deep trench structure, c) The step of performing a second polishing of the polished tapered fiber array lid and placing the further polished fiber array lid in close proximity to the silicon oxide substrate, d) The optical fiber core is positioned close to the silicon oxide substrate in order to achieve good optical interconnection between the fiber array and the wafer substrate. method.
  11. The method according to claim 10 , wherein the taper angle of the further polished fiber array lid is 30° to 45°.
  12. The V-groove array is manufactured on a separate silicon submount. The wafer substrate is edge-coupled by active alignment. The method according to claim 10.

Description

This embodiment generally relates to optical integrated circuits (PICs), and more specifically, to the coupling of optical fiber components and silicon photonics in a PIC. Optical integrated circuits (PICs), also known as integrated optical circuits or planar optical circuits, are devices that integrate many optical and electronic components. PICs are manufactured using lithography on substrates of nonlinear crystalline materials, including silicon, silica, or lithium niobate. PICs primarily consist of arrays of identical components used in optical fiber communications, optical sensors, and measurement applications. In most cases, the substrate material determines the characteristics and limitations of a PIC, such as silica-on-silicon integrated optics built on a silicon wafer. Silica waveguides enable the realization of couplers and filters, splitters, and combiners. They can also include active elements with optical gain connected to optical fibers. One method of coupling multiple waveguides is to use a fiber array. In some cases, the photonic function is directly implemented on the chip. Silicon nitride (Si3N4) platforms are also used to manufacture photonic devices operating in the 1 μm spectral region or shorter wavelengths. Waveguides are also fabricated on silica glass, such as fused silica glass, where the waveguides are fabricated far below the surface, forming embedded waveguides that enable three-dimensional circuit design. Furthermore, another material used as a substrate is lithium niobate (LiNbO3), a nonlinear crystalline material suitable for devices performing nonlinear functions, such as electro-optic modulators or acousto-optic transducers. In complex optical transmission systems, efficient fiber-to-chip coupling is crucial because optical interconnects between fibers and PICs occur frequently throughout the system. However, the dimensional difference between the substrate waveguide and the fiber diameter presents complex challenges. For example, while the feature size of a silicon waveguide is small (tens of nanometers), a typical single-mode fiber (SMF) has a diameter of approximately 125 μm and a core diameter of nearly 10 μm. This results in a large size mismatch between the fiber core and the Si waveguide, and significant optical transmission loss occurs when light emitted from the fiber core directly enters the Si waveguide. Fiber-to-chip couplers are a key optical component that addresses this problem in optical interconnects. Generally, fiber-to-chip coupling can be performed in two ways, depending on the relative position of the fiber and the photonic chip: vertical coupling (or off-plane coupling) and butt coupling (or edge coupling/in-plane coupling). In edge coupling, fibers are typically positioned in wafer facets, aligned horizontally with the Si waveguide, and edge couplers are commonly used. While edge couplers offer high coupling efficiency, wide bandwidth, and polarization independence, they also have some limitations, including a relatively larger footprint than grating couplers, fixed coupling locations, and more stringent requirements for the coupling facets. In telecom and datacom applications, some form of fiber-to-PIC coupling is required for the transfer of optical signals to and from a PIC microcontroller. Edge coupling is one option that can provide low insertion loss (IL), wide spectral bandwidth (BW), and low sensitivity to polarization. However, current standard Si-PICs for edge coupling employ deep trench etching to form a high-quality optical interface for edge coupling, but this process creates protrusions that result in a 20-50 μm gap between the fiber core and the edge coupler. This gap causes high optical power loss. Several solutions have been proposed to avoid the effects of these protrusions. One solution involves longitudinally positioned fibers extending from the V-groove. However, this is a complex process and, coupled with stability issues, does not provide any way to ensure fiber end roughness because fiber end polishing cannot be applied. Yet another solution involves removing the bottom fiber array lid for the fiber array assembly. However, removing the lid complicates the process and increases costs because it loosens control over fiber positioning and epoxy thickness. Other purposes, features, and advantages will be understood by those skilled in the art from the following description of preferred embodiments and the accompanying drawings. Figure 1 shows a typical fiber array-based optical integrated circuit. Figure 2 shows an extended fiber array-based optical integrated circuit. Figure 3 shows a fiber array-based optical integrated circuit without a bottom lid. Figure 4 shows a fiber array having polished tapered lids for bonding fibers to a wafer substrate to form an optical integrated circuit, according to one embodiment of the present invention. In the following detailed description, specific implementable embodiments will be described w