JP-7857476-B2 - Semiconductor equipment

Inventors

• 松嵜 隆徳
• 大貫 達也
• 上妻 宗広
• 青木 健
• 岡本 佑樹
• 池田 隆之

Assignees

• 株式会社半導体エネルギー研究所

Dates

Publication Date

20260512

Application Date

20250527

Priority Date

20200803

Claims (1)

1. A semiconductor device having an analog arithmetic unit and a memory circuit, The memory circuit has a transistor having an oxide semiconductor in the channel formation region. The memory circuit has the function of supplying weight data as analog data to the analog arithmetic unit. The analog arithmetic unit has a function to perform sum-of-accumulate operations using the weight data, The analog arithmetic unit has a first transistor having an oxide semiconductor in the channel formation region, The analog arithmetic unit has the function of flowing a current corresponding to the product of the weight data and the input data between the source and drain of the first transistor, A semiconductor device having the function of operating the first transistor in a subthreshold region and passing a current corresponding to the product between the source and drain of the first transistor.

Description

This specification describes semiconductor devices, etc. Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields related to one aspect of the present invention disclosed herein include semiconductor devices, imaging devices, display devices, light-emitting devices, energy storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input/output devices, methods for driving them, or methods for manufacturing them. Electronic devices containing semiconductor devices, including CPUs (Central Processing Units), are becoming widespread. To process large amounts of data at high speed in such electronic devices, technological development to improve the performance of semiconductor devices is active. One technology that achieves high performance is the so-called SoC (System on Chip), which tightly couples an accelerator such as a GPU (Graphics Processing Unit) with the CPU. However, with SoC-based high-performance semiconductor devices, increased heat generation and power consumption become problematic. In Artificial Intelligence (AI) technology, the computational load increases significantly due to the enormous number of calculations and parameters. This increase in computational load leads to increased heat generation and power consumption, so architectures to reduce computational load are being actively proposed. Representative architectures include Binary Neural Networks (BNN) and Ternary Neural Networks (TNN), which are particularly effective for reducing circuit size and power consumption (see, for example, Patent Document 1). International Publication No. 2019/078924 Figures 1A and 1B illustrate an example of the configuration of a semiconductor device.Figures 2A and 2B illustrate an example of the configuration of a semiconductor device.Figures 3A and 3B illustrate an example of the configuration of a semiconductor device.Figure 4 illustrates an example of a semiconductor device configuration.Figures 5A and 5B illustrate an example of the configuration of a semiconductor device.Figures 6A and 6B illustrate an example of the configuration of a semiconductor device.Figures 7A and 7B illustrate an example of the configuration of a semiconductor device.Figure 8 illustrates an example of a semiconductor device configuration.Figures 9A and 9B illustrate an example of the configuration of a semiconductor device.Figures 10A and 10B illustrate an example of the configuration of a semiconductor device.Figures 11A, 11B, and 11C illustrate examples of semiconductor device configurations.Figure 12 is a diagram illustrating an example of the configuration of a semiconductor device.Figure 13 is a diagram illustrating an example of the configuration of a semiconductor device.Figures 14A and 14B illustrate an example of the configuration of a semiconductor device.Figures 15A and 15B illustrate an example of the configuration of a semiconductor device.Figures 16A and 16B illustrate an example of the configuration of a semiconductor device.Figures 17A and 17B illustrate an example of the configuration of a semiconductor device.Figure 18 illustrates an example of the configuration of a computing system.Figure 19 is a diagram illustrating an example of a CPU configuration.Figures 20A and 20B illustrate an example of a CPU configuration.Figure 21 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device.Figures 22A to 22C are schematic cross-sectional diagrams showing examples of transistor configurations.Figure 23 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device.Figures 24A and 24B are schematic cross-sectional diagrams showing examples of transistor configurations.Figure 25 is a schematic cross-sectional view showing an example of a transistor configuration.Figure 26A illustrates the classification of IGZO crystal structures, Figure 26B illustrates the XRD spectrum of crystalline IGZO, and Figure 26C illustrates the micro-electron diffraction pattern of crystalline IGZO.Figure 27A is a perspective view showing an example of a semiconductor wafer, Figure 27B is a perspective view showing an example of a chip, and Figures 27C and 27D are perspective views showing an example of an electronic component.Figure 28 is a perspective view showing an example of an electronic device.Figures 29A to 29C are perspective views showing an example of an electronic device. The embodiments of the present invention are described below. However, it will be readily apparent to those skilled in the art that one embodiment of the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, one embodiment of the present invention is not to be construed as being limited to the embodiments described below.